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[core] syntax

This commit is contained in:
tangxifan 2023-07-23 22:39:36 -07:00
parent f551188d0f
commit f031148959
3 changed files with 19 additions and 11 deletions
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4
openfpga/src/fabric/build_top_module.cpp
View File

@ -79,8 +79,8 @@ int build_top_module(
} else {
/* TODO: Build the tile instances under the top module */
status = build_top_module_tile_child_instances(
module_manager, top_module, blwl_sr_banks, circuit_lib, grids,
fabric_tile, config_protocol, fabric_key, frame_view, tile_direct, arch_direct, verbose);
module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk, rr_clock_lookup, vpr_device_annotation, grids, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct,
fabric_tile, config_protocol, sram_model, fabric_key, frame_view, verbose);
}
if (status != CMD_EXEC_SUCCESS) {

16
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1692,12 +1692,12 @@ static void add_module_nets_connect_tile_direct_connection(
sink_pin_grid_side, sink_pin_info);
sink_port_name = generate_tile_module_port_name(des_grid_instance_name, sink_port_name);
ModulePortId sink_port_id =
module_manager.find_module_port(sink_tile_module, sink_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sink_tile_module,
module_manager.find_module_port(des_tile_module, sink_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(des_tile_module,
sink_port_id));
VTR_ASSERT(
1 ==
module_manager.module_port(sink_tile_module, sink_port_id).get_width());
module_manager.module_port(des_tile_module, sink_port_id).get_width());
/* Add a submodule of direct connection module to the top-level module */
size_t direct_instance_id =
@ -1756,11 +1756,15 @@ static void add_top_module_nets_connect_tile_direct_connections(
int build_top_module_tile_child_instances(
ModuleManager& module_manager, const ModuleId& top_module,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const CircuitLibrary& circuit_lib, const DeviceGrid& grids,
const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const TileAnnotation& tile_annotation, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
const ArchDirect& arch_direct,
const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model,
const FabricKey& fabric_key, const bool& frame_view,
const TileDirect& tile_direct,
const ArchDirect& arch_direct,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
vtr::Matrix<size_t> tile_instance_ids;

10
openfpga/src/fabric/build_top_module_child_tile_instance.h
View File

@ -35,11 +35,15 @@ namespace openfpga {
int build_top_module_tile_child_instances(
ModuleManager& module_manager, const ModuleId& top_module,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const CircuitLibrary& circuit_lib, const DeviceGrid& grids,
const CircuitLibrary& circuit_lib, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& rr_clock_lookup,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const TileAnnotation& tile_annotation, const RRGraphView& rr_graph,
const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct,
const ArchDirect& arch_direct,
const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
const CircuitModelId& sram_model,
const FabricKey& fabric_key, const bool& frame_view,
const TileDirect& tile_direct,
const ArchDirect& arch_direct,
const bool& verbose);
} /* end namespace openfpga */