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533 Commits

Author SHA1 Message Date
Eddie Hung d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Clifford Wolf 373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff 
Improve pmgen, Add "peepopt" pass with shift-mul pattern
 2019-05-03 20:39:50 +02:00
Clifford Wolf 42190207b4 Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 14:25:01 +02:00
Clifford Wolf 5c2c0b4bb2 Further improve unused-detection for opt_clean driver-driver conflict warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 09:22:26 +02:00
Clifford Wolf f12e1155f1 Improve unused-detection for opt_clean driver-driver conflict warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 09:12:10 +02:00
Clifford Wolf a30b99e66e Silently resolve completely unused cell-vs-const driver-driver conflicts 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:29:34 +02:00
Clifford Wolf 32ff37bb5a Fix segfault in wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 22:20:45 +02:00
Clifford Wolf 9d117eba9d Add handling of init attributes in "opt_expr -undriven" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 14:46:12 +02:00
Clifford Wolf b515fd2d25 Add peepopt_muldiv, fixes #930 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 11:25:15 +02:00
Clifford Wolf 754b1ee4b3 Drive dangling wires with init attr with their init value, fixes #956 2019-04-29 08:44:53 +02:00
Clifford Wolf 71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf 634482380c Preserve $specify[23] cells 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf c84cdc711c Remove some left-over log_dump() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 17:55:41 +02:00
Clifford Wolf 8ed4a53d99
Merge pull request #951 from YosysHQ/clifford/logdebug 
Add log_debug() framework
 2019-04-22 20:09:51 +02:00
Clifford Wolf e158ea2097 Add log_debug() framework 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 17:25:52 +02:00
Clifford Wolf 0f0ada13f4 Add full_pmux feature to pmux2shiftx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 15:26:20 +02:00
Clifford Wolf fc23af1707 Auto-initialize OnehotDatabase on-demand in pmux2shiftx.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 18:13:37 +02:00
Clifford Wolf 97e9caa4fa Add "onehot" pass, improve "pmux2shiftx" onehot handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 17:52:16 +02:00
Clifford Wolf b3a3e08e38 Improve "pmux2shiftx" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 02:03:44 +02:00
Clifford Wolf e06d158e8a Fix some typos 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 01:18:07 +02:00
Clifford Wolf 37728520a6 Improvements in "pmux2shiftx" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 01:15:48 +02:00
Clifford Wolf 0070184ea9 Improvements in pmux2shiftx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Clifford Wolf 177878cbb0 Improve pmux2shift ctrl permutation finder 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Clifford Wolf 481f0015be Complete rewrite of pmux2shiftx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Clifford Wolf 1bf8c2b823 Import initial pmux2shiftx from eddieh 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Clifford Wolf 7cfd83c341 Trim init attributes when resizing FFs in "wreduce", fixes #887 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-22 11:42:19 +01:00
Clifford Wolf f806b95ed6 Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 20:52:00 +01:00
Clifford Wolf e847690bda Fix multiple issues in wreduce FF handling, fixes #835 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-28 17:24:46 -08:00
Clifford Wolf cd722f26a5 Cleanups in ARST handling in wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 20:34:23 +01:00
Keith Rothman 25680f6a07 Fix WREDUCE on FF not fixing ARST_VALUE parameter. 
Adds test case that fails without code change.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-02-22 10:30:42 -08:00
Clifford Wolf 0e371109b0
Merge pull request #818 from YosysHQ/clifford/dffsrfix 
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
 2019-02-21 18:58:44 +01:00
Clifford Wolf 2da4c9c8f0 Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 13:49:45 +01:00
Clifford Wolf 246391200e Add FF support to wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:36:42 +01:00
Clifford Wolf 8a63fc51d3 Bugfix in $memrd sharing 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-07 10:04:47 +01:00
Clifford Wolf d98fe8ce1f
Merge pull request #775 from whitequark/opt_flowmap 
flowmap: new techmap pass
 2019-01-03 17:03:18 +01:00
whitequark 07af772a72 flowmap: new techmap pass. 2019-01-03 14:28:19 +00:00
Clifford Wolf 0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp 
opt_expr: refactor and improve simplification of comparisons
 2019-01-02 17:34:04 +01:00
whitequark bf8db55ef3 opt_expr: improve simplification of comparisons with large constants. 
The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
 2019-01-02 15:45:28 +00:00
Clifford Wolf 2e606b1802
Merge pull request #773 from whitequark/opt_lut_elim_fixes 
opt_lut: elimination fixes
 2019-01-02 15:45:29 +01:00
whitequark efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
whitequark c55dfb8369 opt_lut: reflect changes in sigmap. 
Otherwise, some LUTs will be missed during elimination.
 2019-01-02 10:21:58 +00:00
whitequark 06143ab33f opt_lut: use a worklist, and revisit cells affected by elimination. 2019-01-02 09:36:32 +00:00
whitequark f7363ac508 opt_lut: count eliminated cells, and set opt.did_something for them. 2019-01-02 09:14:43 +00:00
whitequark 4fd458290c opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI. 2019-01-02 05:11:29 +00:00
whitequark 9e9846a6ea opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. 2019-01-02 03:01:25 +00:00
whitequark 8e53d2e0bf opt_expr: simplify any unsigned comparisons with all-0 and all-1. 
Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
 2019-01-02 02:45:49 +00:00
whitequark 42c356c49c opt_lut: eliminate LUTs evaluating to constants or inputs. 2018-12-31 23:55:40 +00:00
Clifford Wolf 0a840dd883 Fix handling of (* keep *) wires in wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-31 16:37:40 +01:00
Clifford Wolf 556341a77f
Merge pull request #720 from whitequark/master 
lut2mux: handle 1-bit INIT constant in $lut cells
 2018-12-16 15:27:23 +01:00
whitequark 7ec740b7ad opt_lut: leave intact LUTs with cascade feeding module outputs. 2018-12-07 17:13:52 +00:00
whitequark 9eb03d458d opt_lut: show original truth table for both cells. 2018-12-07 17:04:41 +00:00
whitequark a8ab722824 opt_lut: add -limit option, for debugging misoptimizations. 2018-12-07 16:36:26 +00:00
Clifford Wolf 643f858acf Bugfix in opt_expr handling of a<0 and a>=0 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-06 07:29:21 +01:00
whitequark 88217d0157 opt_lut: simplify type conversion. NFC. 2018-12-05 19:12:02 +00:00
Clifford Wolf 2d98db73e3 Rename opt_lut.cpp to opt_lut.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-05 18:03:58 +01:00
whitequark 45cb6200af opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. 2018-12-05 16:30:37 +00:00
whitequark e603484070 opt_lut: always prefer to eliminate 1-LUTs. 
These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
 2018-12-05 16:30:37 +00:00
whitequark 59eea0183f opt_lut: collect and display statistics. 2018-12-05 16:30:37 +00:00
whitequark e54c7e951c opt_lut: refactor to use a worker. NFC. 2018-12-05 16:30:37 +00:00
whitequark 9e072ec21f opt_lut: new pass, to combine LUTs for tighter packing. 2018-12-05 16:30:37 +00:00
Clifford Wolf ab97eddee9 Add iteration limit to "opt_muxtree" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-20 17:56:47 +01:00
Henner Zeller 3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf 587056447e Add optimization of tristate buffer with constant control input 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 15:18:27 +02:00
Clifford Wolf fba499b866 Fix opt_rmdff handling of $dlatchsr 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-26 11:46:05 +01:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf ca2adc30c9 Add warnings for driver-driver conflicts between FFs (and other cells) and constants 2017-12-12 17:13:27 +01:00
Clifford Wolf c238f45ecf Fix memory corruption bug in opt_rmdff 2017-10-26 18:02:15 +02:00
Clifford Wolf 1e502ef5a0 Fix typo in opt_clean log message 2017-10-26 18:01:48 +02:00
Kaj Tuomi e558b3284b Fix input vector for reduce cells. Infinite loop fixed. 2017-10-17 09:58:01 +03:00
Clifford Wolf 716dbc9274 Revert 90be0d8 as it causes endless loops for some designs 2017-10-14 11:57:25 +02:00
Kaj Tuomi 90be0d800b Fix input vector for reduce cells. 2017-10-12 13:05:10 +03:00
Andrew Zonenberg 66e8986ae7 Minor changes to opt_demorgan requested during code review 2017-09-14 10:35:25 -07:00
Andrew Zonenberg 6da5d36968 Initial version of opt_demorgan is functioning for AND/OR gates. Not the prettiest results for bus inputs, but this can be improved 2017-09-12 18:47:46 -07:00
Clifford Wolf 68c42f3a19 Don't track , ... contradictions through x/z-bits 2017-08-25 16:18:17 +02:00
Clifford Wolf db6d78a186 Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr 2017-08-25 16:02:15 +02:00
Clifford Wolf 88983f5012 Mostly coding style related fixes in rmports pass 2017-08-15 11:32:35 +02:00
Andrew Zonenberg 15e41d6363 rmports: Now remove ports from cell instances if we optimized them out of that cell 2017-08-14 11:44:05 -07:00
Andrew Zonenberg 0ee27d0226 ProcessModule is no longer virtual (why was it in the first place?) 2017-08-14 11:18:09 -07:00
Andrew Zonenberg bd2ac68769 rmports now works on all modules in the design, not just the top. 2017-08-14 11:16:44 -07:00
Andrew Zonenberg d5e5bbad86 Updated Makefile to reflect opt_rmports being renamed to rmports 2017-08-14 11:04:56 -07:00
Andrew Zonenberg 1a6a23f91a Renamed opt_rmports pass to rmports 2017-08-14 11:00:45 -07:00
Andrew Zonenberg 1bb150c231 Improved handling of constant connections in opt_rmports 2017-08-14 10:28:19 -07:00
Andrew Zonenberg 2877d5e504 Fixed handling of cell ports that aren't wires 2017-08-14 10:28:16 -07:00
Andrew Zonenberg 3dd7f42e2b opt_rmports: Fixed incorrect handling of multi-bit nets 2017-08-14 10:28:11 -07:00
Andrew Zonenberg 66aac06eee Removed commented out debug code 2017-08-14 10:28:04 -07:00
Andrew Zonenberg cca3cb5fbb Added opt_rmports pass (remove unconnected ports from top-level modules) 2017-08-14 10:27:59 -07:00
Clifford Wolf 007f29b9c2 Add support for set-reset cell variants to opt_rmdff 2017-08-09 13:29:52 +02:00
Clifford Wolf c4a7958f70 Add handling of constant reset signals to opt_rmdff 2017-08-06 13:27:18 +02:00
Clifford Wolf e7d1277a2c Add consolidation of init attributes to opt_clean, some opt_clean log fixes 2017-07-29 00:10:33 +02:00
Clifford Wolf 649bb9374f Add "opt_expr -fine" feature to remove neutral bits from reduce and logic operators 2017-07-26 18:28:55 +02:00
Salvador E. Tropea ca23554528 Excluded $_TBUF_ from opt_merge pass 2017-07-03 13:21:20 -03:00
Clifford Wolf 0a02cdb93b Fix and_or_buffer optimization in opt_expr for signed operators 2017-07-01 16:05:26 +02:00
Clifford Wolf 18c030a8c9 Add $tribuf to opt_merge blacklist 2017-06-30 17:44:44 +02:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
Clifford Wolf 180d704568 Disable opt_merge for $anyseq and $anyconst 2017-02-28 22:17:00 +01:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf 95dae6d416 Fixed some "used uninitialized" warnings in opt_expr 2017-02-11 10:50:48 +01:00
Clifford Wolf a5bfeb9e07 Add optimization of (a && 1'b1) and (a || 1'b0) 2017-02-11 10:05:00 +01:00
C-Elegans 94b272077d Fix issue #306, "Bug in opt -full" 
Add check for whether the high bit in the constant expression is greater
than the width of the variable, and optimizes that to a constant 1 or
0
 2017-02-10 10:38:02 -05:00
Clifford Wolf e6cc67b46f Fix handling of init attributes with strange width 2017-02-09 16:06:58 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf ffbe8d41f3 Fix indenting and log messages in code merged from opt_compare_pr 2017-01-31 16:20:56 +01:00
Clifford Wolf 19a980277f Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans-opt_compare_pr 2017-01-31 15:54:41 +01:00
Clifford Wolf 7481ba4750 Improve opt_rmdff support for $dlatch cells 2017-01-31 10:15:04 +01:00
C-Elegans a94c3694d7 Refactor and generalize the comparision optimization 
Generalizes the optimization to:
a < C,
a >= C,
C > a,
C <= a
 2017-01-30 17:52:16 -05:00
C-Elegans 2fa0fd4a37 Do not use b.as_int() in calculation of bit set 2017-01-21 12:58:26 -05:00
C-Elegans 84f9cd0025 Optimize compares to powers of 2 
Remove opt_compare and put comparison pass in opt_expr

assuming a [7:0] is unsigned
a >= (1<<x) becomes |a[7:x]
a <  (1<<x) becomes !a[7:x]

Additionally:
a >= 0 becomes constant true,
a < 0 becomes constant false

delete opt_compare.cc
revert opt.cc to commit b7cfb7dbd (remove opt_compare step)
 2017-01-16 13:45:50 -05:00
C-Elegans 943389cdd5 Fix issue #269, optimize signed compare with 0 
add opt_compare pass and add it to opt
for a < 0:
    if a is signed, replace with a[max_bit-1]
for a >= 0:
    if a is signed, replace with ~a[max_bit-1]
 2017-01-15 13:38:29 -05:00
Clifford Wolf 2ef454c3f5 Added opt_rmdff support for $ff cells 2016-10-14 13:02:36 +02:00
Clifford Wolf ed519f578e Added "opt_rmdff -keepdc" 2016-09-30 17:02:38 +02:00
Clifford Wolf 4ea7054b56 Improved init spec handling in opt_rmdff, modernized the code a bit 2016-08-30 01:34:04 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf d77a914683 Added "wreduce -memx" 2016-08-20 12:52:50 +02:00
Clifford Wolf f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end 2016-08-19 18:38:25 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf 11f7b8a2a1 Added opt_expr support for div/mod by power-of-two 2016-05-29 12:17:36 +02:00
Clifford Wolf 0d2923cccd Connections between inputs and inouts are driven by the input 2016-04-26 19:49:05 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf 1565d1af69 Fixed performance bug in "share" pass 2016-04-21 19:47:25 +02:00
Clifford Wolf f38ca3e18f Improvements in opt_expr 2016-04-21 14:23:04 +02:00
Clifford Wolf 6cafd08ac1 Improved opt_merge support for $pmux cells 2016-03-31 09:58:55 +02:00
Clifford Wolf e2f6d61c00 Typo fixes in opt_expr and opt_merge 2016-03-31 09:56:56 +02:00
Clifford Wolf ec93680bd5 Renamed opt_share to opt_merge 2016-03-31 08:52:49 +02:00
Clifford Wolf 1d0f0d668a Renamed opt_const to opt_expr 2016-03-31 08:46:56 +02:00
Andrew Zonenberg dd7204c0bd Fixed typo in log message 2016-03-30 20:30:03 -07:00
Clifford Wolf d6592d5b99 Use alphanumerical order instead of idstring idx in opt_clean compare_signals() 2016-02-02 09:16:18 +01:00
Clifford Wolf ccdbf41be6 Improvements in wreduce 2015-10-31 13:39:30 +01:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf 2a0f577f83 Fixed handling of driver-driver conflicts in wreduce 2015-10-24 13:44:35 +02:00
Clifford Wolf 1d83854d84 Bugfixes in handling of "keep" attribute on wires 2015-10-15 14:57:28 +02:00
Clifford Wolf 82028c42e0 Added wreduce $mul support and fixed signed $mul opt_const bug 2015-09-25 17:27:06 +02:00
Clifford Wolf 51e1295d79 Added detection of "mux inverter" chains in opt_const 2015-09-18 11:55:31 +02:00
Clifford Wolf e7c018e5d1 Fixed sharing of $memrd cells 2015-09-12 16:01:20 +02:00
Clifford Wolf b10ea0550d gcc-4.6 build fixes 2015-09-01 12:51:23 +02:00
Clifford Wolf f43815054e Properly clean up unused "init" attributes 2015-08-18 13:50:15 +02:00
Clifford Wolf ae09c89f62 Fixed opt_clean handling of inout ports 2015-08-16 09:50:17 +02:00
Clifford Wolf 84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf c43f38c81b Improved handling of "keep" attributes in hierarchical designs in opt_clean 2015-08-12 14:10:14 +02:00
Clifford Wolf 667b015018 Merge pull request #70 from gaomy3832/bugfix 
Remove unused blackbox modules in opt_clean.
 2015-08-12 08:45:04 +02:00
Mingyu Gao cbda56d178 Remove unused blackbox modules in opt_clean. 2015-08-11 09:51:08 -07:00
Mingyu Gao 8c4c62f3e1 Bugfix for cell hash cache option in opt_share. 2015-08-11 11:40:23 +02:00
Clifford Wolf 2185125760 Added missing ct_all setup to opt_clean 2015-08-11 07:54:32 +02:00
Mingyu Gao 021b4a2436 Bugfix for cell hash cache option in opt_share. 2015-08-10 13:01:44 -07:00
Clifford Wolf 2a613b1b66 Some cleanups in opt_rmdff 2015-07-25 12:09:57 +02:00
Clifford Wolf 914ae3401e Improved $adff simplification 2015-07-24 14:12:50 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 053058d781 Added opt_const -clkinv 2015-07-01 10:49:21 +02:00
Clifford Wolf 08f9b38a9c Added opt_share -share_all 2015-05-31 14:24:34 +02:00
Clifford Wolf 4b6221478e Added simple $dlatch support to opt_rmdff 2015-05-23 09:45:48 +02:00
Clifford Wolf e122c2644e preserve used $-wires with init attribute in opt_clean 2015-05-22 08:20:29 +02:00
Clifford Wolf f483dce7c2 Added $eq/$neq -> $logic_not/$reduce_bool optimization 2015-04-29 07:28:15 +02:00
Clifford Wolf 9041f34233 Improved handling of init values in opt_rmdff 
based on a patch by Mingyu Gao, user gaomy3832 on github
 2015-04-18 08:04:31 +02:00
Clifford Wolf e305d85807 Added handling of bool-output cells to "wreduce" 2015-04-13 19:27:49 +02:00
Clifford Wolf 1f1deda888 Added non-std verilog assume() statement 2015-02-26 18:47:39 +01:00
Clifford Wolf 9ae21263f0 Some cleanups in "clean" 2015-02-24 22:31:30 +01:00
Clifford Wolf 4e6ca7760f Replaced ezDefaultSAT with ezSatPtr 2015-02-21 12:15:41 +01:00
Clifford Wolf 024aa559e2 wreduce help typo fix 2015-02-17 13:02:16 +01:00
Clifford Wolf 0748ef638d Bugfix in wreduce 2015-02-16 09:08:00 +01:00
Clifford Wolf 910556560f Added $meminit cell type 2015-02-14 10:23:03 +01:00
Clifford Wolf 87819c62fa Less aggressive "share" defaults 2015-02-10 20:51:37 +01:00
Clifford Wolf 8805c24640 Fixed opt_clean performance bug 2015-02-04 16:34:06 +01:00
Clifford Wolf a8f4a099b5 Using design->selected_modules() in opt_* 2015-02-03 23:45:01 +01:00
Clifford Wolf 8dfa105255 Bugfix in opt_const $eq -> buffer code 2015-01-31 23:25:32 +01:00
Clifford Wolf 2a9ad48eb6 Added ENABLE_NDEBUG makefile options 2015-01-24 12:16:46 +01:00
Clifford Wolf 43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf 74e1de1fac Fixed opt_muxtree performance bug 2015-01-21 16:44:07 +01:00
Clifford Wolf f630868bc9 Improvements in opt_muxtree 2015-01-18 12:57:36 +01:00
Clifford Wolf d3b35017f8 More opt_muxtree cleanups 2015-01-18 12:13:18 +01:00
Clifford Wolf 61192514e3 Various cleanups and improvements in opt_muxtree 2015-01-18 11:17:56 +01:00
Clifford Wolf a95c229e12 Fixed a bug in opt_muxtree for "mux forests" 2015-01-17 13:56:53 +01:00
Clifford Wolf 3628ca989c Improved opt_muxtree 2015-01-17 12:05:19 +01:00
Clifford Wolf 8426884b40 Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim) 2015-01-13 13:20:09 +01:00
Clifford Wolf fd787609aa disabled problematic mux -> and/or transform 2015-01-07 23:25:51 +01:00
Clifford Wolf 462b22f44f dict<> ref vs insert bugfix 2015-01-06 00:16:44 +01:00
Clifford Wolf 11c3b81c08 typo fix for "opt -fast" 2014-12-30 22:35:38 +01:00
Clifford Wolf c64b1de11d Fixed build with SMALL=1 2014-12-30 11:41:24 +01:00
Clifford Wolf 29a555ec7e Added statehash to ezSAT 2014-12-29 17:10:37 +01:00
Clifford Wolf 3ff0d04555 Cleanups in opt_clean 2014-12-29 05:11:06 +01:00
Clifford Wolf 7d843adef9 dict/pool changes in opt_clean 2014-12-29 04:06:52 +01:00
Clifford Wolf cfe0817697 Converting "share" to dict<> and pool<> complete 2014-12-29 02:01:42 +01:00
Clifford Wolf 9ff3a9f30d Switched most of "share" to dict<> and pool<> 2014-12-29 00:42:48 +01:00
Clifford Wolf 445686cba3 using dict and pool in opt_reduce 2014-12-28 21:27:05 +01:00
Clifford Wolf 951c72ba52 bugfix in opt_share 2014-12-28 21:26:36 +01:00
Clifford Wolf 3da46d3437 Renamed hashmap.h to hashlib.h, some related improvements 2014-12-28 17:51:16 +01:00
Clifford Wolf 6c8b0a5fd1 More dict/pool related changes 2014-12-27 12:02:57 +01:00
Clifford Wolf 66ab88d7b0 More hashtable finetuning 2014-12-27 03:04:50 +01:00
Clifford Wolf ec4751e55c Replaced std::unordered_set (nodict) with Yosys::pool 2014-12-26 21:59:41 +01:00
Clifford Wolf 9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf edb3c9d0c4 Renamed extend() to extend_xx(), changed most users to extend_u0() 2014-12-24 09:51:17 +01:00
Clifford Wolf 546e8b5fe7 Improved TopoSort determinism 2014-11-07 15:21:03 +01:00
Clifford Wolf ab28491f27 Added "opt -full" alias for all more aggressive optimizations 2014-10-31 03:36:51 +01:00
Clifford Wolf 84ffe04075 Fixed various VS warnings 2014-10-18 15:20:38 +02:00
Clifford Wolf 18cb8b4636 Don't be too smart with $dff cells with "init" attribute on out signal 2014-10-16 11:49:31 +02:00
Clifford Wolf 66eb254fc2 Some cleanups in opt_clean 2014-10-16 11:46:57 +02:00
William Speirs 6433203b39 Wrapped init in std::set constructor 2014-10-15 00:58:05 +02:00
Clifford Wolf 35fbc0b35f Do not the 'z' modifier in format string (another win32 fix) 2014-10-11 11:42:08 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf c5c7066ea6 sat encoding for exclusive $pmux ctrl inputs in "share" pass 2014-10-03 19:01:24 +02:00
Clifford Wolf 3e4b0cac8d added resource sharing of $macc cells 2014-10-03 12:58:40 +02:00
Clifford Wolf c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf 600c6cb013 remove buffers in opt_clean 2014-10-03 10:04:15 +02:00
Clifford Wolf 7019bc00e4 resource sharing of $alu cells 2014-10-03 09:55:50 +02:00
Clifford Wolf 0b8cfbc6fd Added support for "keep" on modules 2014-09-29 12:51:54 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf 13117bb346 Re-enabled assert for new logic loops in "share" pass 2014-09-21 19:44:08 +02:00
Clifford Wolf 96e821dc6c Various improvements regarding logic loops in "share" results 2014-09-21 19:36:56 +02:00
Clifford Wolf d6e2ace95b Logic loop bugfix for "share" pass 2014-09-21 15:13:44 +02:00
Clifford Wolf b28be0759f Added "share -limit" 2014-09-21 15:13:06 +02:00
Clifford Wolf a6c08b40fe Still loop bug in "share": changed assert to warning 2014-09-21 14:51:07 +02:00
Clifford Wolf 8d60754aef Do not introduce new logic loops in "share" 2014-09-21 13:52:39 +02:00
Clifford Wolf edf11c635a Assert on new logic loops in "share" pass 2014-09-21 12:57:33 +02:00
Clifford Wolf 2cbdbaad1f Fixed wreduce $shiftx handling 2014-09-15 11:29:09 +02:00
Clifford Wolf aab0e3bf70 Cleanup in wreduce 2014-09-14 10:01:30 +02:00
Ruben Undheim 79cbf9067c Corrected spelling mistakes found by lintian 2014-09-06 08:47:06 +02:00
Clifford Wolf f5a40e7043 Fixed "opt_const -fine" for $pos cells 2014-09-04 08:55:58 +02:00
Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
Clifford Wolf d5148f2e01 Moved "share" and "wreduce" to passes/opt/ 2014-09-01 11:45:26 +02:00
Clifford Wolf e07698818d Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
Clifford Wolf 2a1b08aeb3 Added design->scratchpad 2014-08-30 19:37:12 +02:00
Clifford Wolf 7bbbe3580d Optimize shift ops with constant rhs in opt_const 2014-08-24 17:08:43 +02:00
Clifford Wolf 641501203c Added some additional log messages to opt_const 2014-08-24 17:08:43 +02:00
Clifford Wolf 410d043dd8 Renamed toposort.h to utils.h 2014-08-17 00:55:35 +02:00
Clifford Wolf eb17fbade5 Added "opt -fast" 2014-08-16 15:34:15 +02:00
Clifford Wolf f092b50148 Renamed $_INV_ cell type to $_NOT_ 2014-08-15 14:11:40 +02:00
Clifford Wolf ca87116449 More idstring sort_by_* helpers and fixed tpl ordering in techmap 2014-08-15 02:40:46 +02:00
Clifford Wolf 13f2f36884 RIP $safe_pmux 2014-08-14 11:39:46 +02:00
Clifford Wolf 8fd1c269ac Fixed a performance bug in opt_reduce 2014-08-02 15:12:16 +02:00
Clifford Wolf b9bd22b8c8 More cleanups related to RTLIL::IdString usage 2014-08-02 13:19:57 +02:00
Clifford Wolf bd74ed7da4 Replaced sha1 implementation 2014-08-01 19:01:10 +02:00
Clifford Wolf cdae8abe16 Renamed port access function on RTLIL::Cell, added param access functions 2014-07-31 16:38:54 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 0c86d6106c Added SigPool::check(bit) 2014-07-27 15:38:02 +02:00
Clifford Wolf 77a1462f2d Fixed bug in opt_clean 2014-07-27 15:13:29 +02:00
Clifford Wolf d07a871d35 Improved performance of opt_const on large modules 2014-07-27 14:50:25 +02:00
Clifford Wolf dbb3556e3f Fixed a bug in opt_clean and some RTLIL API usage cleanups 2014-07-27 13:19:05 +02:00
Clifford Wolf 49f72421d5 Using new obj iterator API in a few places 2014-07-27 11:32:42 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf 946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf 3f4e3ca8ad More RTLIL::Cell API usage cleanups 2014-07-26 16:14:02 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf 0520bfea89 Fixed memory corruption in "opt_reduce" pass 2014-07-25 12:49:51 +02:00