ca5f5ffcd6
Merge pull request #2615 from zachjs/genrtlil-conflict
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genrtlil: improve name conflict error messaging
2021-03-01 08:10:19 -08:00
0f5b646ab8
sv: extended support for integer types
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- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
2021-02-28 16:31:56 -05:00
bbff844acd
genrtlil: improve name conflict error messaging
2021-02-26 18:08:23 -05:00
04b41ed04a
Implement $countones, $isunknown and $onehot{,0}
2021-02-26 12:28:58 -05:00
8434ba5a3b
Implement $countbits function
2021-02-26 12:28:58 -05:00
22bed38540
Extend simplify() recursion warning
2021-02-26 12:11:23 -05:00
58a5755187
Merge pull request #2554 from hzeller/master
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Fix digit-formatting calculation for small numbers.
2021-02-25 13:54:16 -08:00
a651204efa
Fix handling of unique/unique0/priority cases in the frontend.
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Basically:
- priority converts to (* full_case *)
- unique0 converts to (* parallel_case *)
- unique converts to (* parallel_case, full_case *)
Fixes #2596 .
2021-02-25 21:53:58 +01:00
dcd9f0af23
Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off ( #2566 )
2021-02-24 15:48:15 -05:00
f4f471f342
frontend: Make helper functions for printing locations.
2021-02-23 23:51:52 +01:00
ad2960adb7
Merge pull request #2594 from zachjs/func-arg-width
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verilog: fix sizing of constant args for tasks/functions
2021-02-23 21:46:16 +00:00
cc7d18d29a
frontend: json: parse negative values
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-02-23 00:26:11 +01:00
01ccb80b70
Merge pull request #2586 from zachjs/tern-recurse
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verilog: support recursive functions using ternary expressions
2021-02-21 20:56:04 +00:00
b6af90fe20
verilog: fix sizing of constant args for tasks/functions
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- Simplify synthetic localparams for normal calls to update their width
- This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
- `eval_const_function` never correctly handled this, but the issue
was not exposed in the existing tests until the recent change to
always attempt constant function evaluation when all-const args
are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases
2021-02-21 15:44:43 -05:00
220cb1f7bb
verilog: error on macro invocations with missing argument lists
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This would previously complain about an undefined internal macro if the
unapplied macro had not already been used. If it had, it would
incorrectly use the arguments from the previous invocation.
2021-02-19 09:18:41 -05:00
27d7741540
Merge pull request #2574 from dh73/master
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Accept disable case for SVA liveness properties.
2021-02-15 17:49:11 +01:00
8de2e863af
verilog: support recursive functions using ternary expressions
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This adds a mechanism for marking certain portions of elaboration as
occurring within unevaluated ternary branches. To enable elaboration of
the overall ternary, this also adds width detection for these
unelaborated function calls.
2021-02-12 14:43:42 -05:00
13c2fd7137
Ganulate Verific support
2021-02-12 10:08:43 +01:00
326f1c9db4
Merge pull request #2573 from zachjs/repeat-call
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verilog: refactored constant function evaluation
2021-02-11 19:56:41 +00:00
73d611990d
Merge pull request #2578 from zachjs/genblk-port
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verlog: allow shadowing module ports within generate blocks
2021-02-11 10:26:49 -05:00
7533534429
Add missing is_signed to type_atom
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-11 15:05:38 +01:00
1d5f3fe506
verlog: allow shadowing module ports within generate blocks
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This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
2021-02-07 11:48:39 -05:00
4b2f977331
genrtlil: fix signed port connection codegen failures
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This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
2021-02-05 19:51:30 -05:00
c96eb2fbd7
Accept disable case for SVA liveness properties.
2021-02-04 15:35:35 -06:00
98c4feb72f
Add check of begin/end labels for genblock
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-02-04 17:16:30 +01:00
b93b6f4285
verilog: refactored constant function evaluation
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Elaboration now attempts constant evaluation of any function call with
only constant arguments, regardless of the context or contents of the
function. This removes the concept of "recommended constant evaluation"
which previously applied to functions with `for` loops or which were
(sometimes erroneously) identified as recursive. Any function call in a
constant context (e.g., `localparam`) or which contains a constant-only
procedural construct (`while` or `repeat`) in its body will fail as
before if constant evaluation does not succeed.
2021-02-04 10:18:27 -05:00
baf1875307
Merge pull request #2529 from zachjs/unnamed-genblk
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verilog: significant block scoping improvements
2021-02-04 09:57:28 +00:00
5eff0b73ae
Provide an integer implementation of decimal_digits().
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Signed-off-by: Henner Zeller <h.zeller@acm.org>
2021-02-01 11:23:44 -08:00
fe74b0cd95
verilog: significant block scoping improvements
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This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
d99c032c27
Require latest Verific build
2021-01-30 09:23:46 +01:00
a4c04d1b90
ast: fix dump_vlog display of casex/casez
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The first child of AST_CASE is the case expression, it's subsequent
childrean that are AST_COND* and can be used to discriminate the type of
the case.
2021-01-29 16:28:15 +01:00
27257a419f
verilog: strip leading and trailing spaces in macro args
2021-01-28 11:26:35 -05:00
ffbd813a8c
Merge pull request #2550 from zachjs/macro-arg-spaces
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verilog: allow spaces in macro arguments
2021-01-25 10:36:07 +00:00
09311b6581
dpi: Support for chandle type
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Signed-off-by: David Shah <dave@ds0.me>
2021-01-23 22:24:31 +00:00
7d014902ec
Fix digit-formatting calculation for small numbers.
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Calling log10() on zero causes a non-sensical value to be calculated. On some
compile options, I've observed yosys crashing with an illegal
instruction (SIGILL).
To make it safe, fix the calculation to do a range check; wrap it a
decimal_digits() function, and use it where the previous ceil(log10(n)) call
was used. As a side, it also improves readability.
Signed-off-by: Henner Zeller <h.zeller@acm.org>
2021-01-21 12:20:53 -08:00
1096b969ef
Allow combination of rand and const modifiers
2021-01-21 08:42:05 -07:00
acad7a6e40
Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-01-20 20:48:10 +01:00
006c18fc11
sv: fix support wire and var data type modifiers
2021-01-20 09:16:21 -07:00
4fadcc8f25
verilog: allow spaces in macro arguments
2021-01-20 08:49:58 -07:00
61501e3266
Fix input/output attributes when resolving typedef of wire
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-01-18 17:31:22 +01:00
09071afe15
Parse package user type in module port list
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-01-18 17:31:22 +01:00
3a8eecebba
Fix indents.
2021-01-04 00:17:16 -08:00
bb3439562e
Add -nosynthesis flag for read_verilog command.
2021-01-04 00:11:01 -08:00
bc2de4567c
Merge pull request #2518 from zachjs/recursion
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verilog: improved support for recursive functions
2021-01-01 09:32:26 +00:00
2085d9a55d
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
75abd90829
sv: complete support for implied task/function port directions
2020-12-31 16:17:13 -07:00
750831e3e0
Fix elaboration of whole memory words used as indices
2020-12-26 21:47:38 -07:00
1419c8761c
Fix constants bound to redeclared function args
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The changes in #2476 ensured that function inputs like `input x;`
retained their single-bit size when instantiated with a constant
argument and turned into a localparam. That change did not handle the
possibility for an input to be redeclared later on with an explicit
width, such as `integer x;`.
2020-12-26 08:48:01 -07:00
deff6a9546
Merge pull request #2501 from zachjs/genrtlil-tern-sign
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genrtlil: fix mux2rtlil generated wire signedness
2020-12-23 23:15:56 +00:00
8ef6b77dc3
Merge pull request #2476 from zachjs/const-arg-width
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Fix constants bound to single bit arguments (fixes #2383 )
2020-12-23 23:15:30 +00:00
999eec5617
genrtlil: fix mux2rtlil generated wire signedness
2020-12-22 17:49:16 -07:00
8206546c45
Fix constants bound to single bit arguments ( fixes #2383 )
2020-12-22 17:01:03 -07:00
3e67ab1ebb
Merge pull request #2479 from zachjs/const-arg-hint
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Allow constant function calls in constant function arguments
2020-12-22 01:31:25 +00:00
0d8e5d965f
Sign extend port connections where necessary
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- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
signedness information
- Resolves #1418
- Resolves #2265
2020-12-18 20:33:14 -07:00
186d6df4c3
Allow constant function calls in constant function arguments
2020-12-07 13:53:27 -07:00
90724ea9e7
Merge pull request #2456 from Zottel/master
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Return correct modname when found in cache.
2020-12-02 22:20:02 +00:00
1c4a18f66f
Bump required Verific version
2020-12-02 15:18:04 +01:00
c1f6ce8b33
Fix SYNTHESIS always being defined in Verilog frontend
2020-12-01 01:37:19 +00:00
2e23dfd96b
Return correct modname when found in cache.
2020-11-26 13:31:22 +01:00
015b476e56
rtlil: remove dotted identifiers.
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No one knows where they came from and they never did anything useful.
2020-11-25 16:47:20 +00:00
c228cb74d6
Update verific version
2020-10-30 08:32:59 +01:00
acc9d0575b
Fix argument handling in connect_rpc
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Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
2020-10-19 13:40:57 +02:00
c8f052bbe0
extend verific library API for formal apps and generators
2020-10-12 14:56:15 +02:00
1b7ed719a5
Update required Verific version
2020-10-05 13:27:27 +02:00
46f0932c4c
Ignore empty parameters in Verilog module instantiations
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Fixes #2394
Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
2020-10-01 18:27:16 +02:00
7e2fc2eaeb
Merge pull request #2378 from udif/pr_dollar_high_low
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Added $high(), $low(), $left(), $right()
2020-10-01 18:17:36 +02:00
a44c5df259
use sha1 for parameter list in case if they contain spaces
2020-09-30 09:16:59 +02:00
44705102b5
Better error for unsupported SVA sequence
2020-09-18 17:08:00 +02:00
f176bd7778
Merge pull request #2329 from antmicro/arrays-fix-multirange-size
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Rewrite multirange arrays sizes [n] as [n-1:0]
2020-09-17 18:27:05 +02:00
9e937961dc
Merge pull request #2330 from antmicro/arrays-fix-multirange-access
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Fix unsupported subarray access detection
2020-09-17 18:21:53 +02:00
7ed0e23e19
We can now handle array slices (e.g. $size(x[1]) etc. )
2020-09-17 00:55:17 +03:00
6de7ba02e3
Fixed comments, removed debug message
2020-09-16 10:57:06 +03:00
b548722bee
Added $high(), $low(), $left(), $right()
2020-09-15 20:49:52 +03:00
3f27a4ea68
Use latest verific
2020-09-02 10:22:25 +02:00
a10893072b
Merge pull request #2352 from zachjs/const-func-localparam
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Allow localparams in constant functions
2020-09-01 17:31:48 +02:00
c1a6097376
Merge pull request #2366 from zachjs/library-format
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Simple support for %l format specifier
2020-09-01 17:30:36 +02:00
3e1840d036
Merge pull request #2353 from zachjs/top-scope
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Module name scope support
2020-09-01 17:30:09 +02:00
452442ac2f
Merge pull request #2365 from zachjs/const-arg-loop-split-type
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Fix constant args used with function ports split across declarations
2020-09-01 17:28:35 +02:00
04d5692a85
Reorder to prevent crash
2020-08-31 12:22:26 +02:00
3af499c60f
ast recognize lower case x and z and verific gives upper case
2020-08-30 13:33:03 +02:00
2f93579bd1
Do not check for 1 and 0 only
2020-08-30 13:15:06 +02:00
b1e3bc059c
Fix import of VHDL enums
2020-08-30 12:25:23 +02:00
c7ceed3fd3
Simple support for %l format specifier
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Yosys doesn't support libraries, so this provides the same behavior as
%m, as some other tools have opted to do.
2020-08-29 13:33:31 -04:00
ecc5c23b4d
Fix constant args used with function ports split across declarations
2020-08-29 13:31:02 -04:00
00e7dec7f5
Replace "ILANG" with "RTLIL" everywhere.
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The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
fe8226a22d
Add formal apps and template generators
2020-08-26 10:39:57 +02:00
6127f22788
Module name scope support
2020-08-20 20:15:08 -04:00
74abc3bbfd
Allow localparams in constant functions
2020-08-20 20:10:24 -04:00
87b9ee330d
Merge pull request #2122 from PeterCrozier/struct_array2
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Support 2D bit arrays in structures. Optimise array indexing.
2020-08-19 17:58:37 +02:00
22765ef0a5
Merge pull request #2339 from zachjs/display-format-0s
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Allow %0s $display format specifier
2020-08-18 17:39:01 +02:00
4aa0dc4dc7
Merge pull request #2338 from zachjs/const-branch-finish
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Propagate const_fold through generate blocks and branches
2020-08-18 17:38:07 +02:00
a9681f4e06
Merge pull request #2317 from zachjs/expand-genblock
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Fix generate scoping issues
2020-08-18 17:37:11 +02:00
7f767bf2b7
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-08-18 17:29:49 +02:00
5ee9349647
Merge pull request #2281 from zachjs/const-real
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Allow reals as constant function parameters
2020-08-18 17:22:20 +02:00
2ee0b8ebea
Propagate const_fold through generate blocks and branches
2020-08-09 17:21:08 -04:00
96ec9acf84
Allow %0s $display format specifier
2020-08-09 17:19:49 -04:00
ba08c25133
Fix subarray access condition
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 16:16:04 +02:00
83ddc62034
Rewrite multirange arrays sizes [n] as [n-1:0]
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-08-03 14:48:27 +02:00
c3e95eb1ab
Fix generate scoping issues
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- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214 , resolves #1456
2020-07-31 20:32:47 -06:00
cc02d58194
Clear last error message
2020-07-29 15:28:33 +02:00
45e96d5d87
Merge pull request #2301 from zachjs/for-loop-errors
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Clearer for loop error messages
2020-07-28 14:07:26 +02:00
58da181af9
Clearer for loop error messages
2020-07-25 10:37:16 -06:00
f69daf4830
Allow blocks with declarations within constant functions
2020-07-25 10:16:12 -06:00
59c4ad8ed3
Avoid generating wires for function args which are constant
2020-07-24 21:18:24 -06:00
f285f7b769
Allow reals as constant function parameters
2020-07-19 20:27:09 -06:00
51ee0b683f
Treat all bison warnings as errors in verilog front-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:57:31 +02:00
7a79843cc3
Use %precedence in verilog_parser.y
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:54:28 +02:00
24540291c7
Fix bison warnings for missing %empty
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:50:59 +02:00
1f4e452609
Run bison with -Wall for verilog front-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-15 11:49:36 +02:00
021ce8e596
Merge pull request #2257 from antmicro/fix-conflicts
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Restore #2203 and #2244 and fix parser conflicts
2020-07-15 11:49:09 +02:00
02c071888b
Add missing semicolons
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-07-15 10:15:13 +02:00
f9ed09423e
Add AST_EDGE support to AstNode::detect_latch(), fixes #2241
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-10 18:41:13 +02:00
d77b3305d8
Fix S/R conflicts
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This commit fixes S/R conflicts introduced by commit 6f9be93
2020-07-10 15:03:53 +02:00
0ffaddee5e
Fix R/R conflicts
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This commit fixes R/R conflicts introduced by commit 7e83a51
2020-07-10 15:03:01 +02:00
de649b9194
Revert "Revert PRs #2203 and #2244."
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This reverts commit 9c120b89ac
2020-07-10 09:59:48 +02:00
dc35ef05f9
verilog_parser: turn S/R and R/R conflicts into hard errors.
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Fixes #2253 .
2020-07-09 19:36:59 +00:00
9c120b89ac
Revert PRs #2203 and #2244 .
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This reverts commit 7e83a51fc9b422f2e4d07cb56f34b06f9be939bd76a34dc5f3
2020-07-09 19:36:32 +00:00
7e83a51fc9
Support logic typed parameters
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-07-06 09:18:48 +02:00
3d8d98d709
Merge pull request #2132 from YosysHQ/eddie/verific_initial
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verific: rewrite initial assume/asserts prior to elaboration
2020-07-02 17:50:22 +02:00
7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar
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Signed and macro grammar update
2020-07-01 16:41:32 +02:00
8ce4f8790e
Merge pull request #2179 from splhack/static-cast
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Support SystemVerilog Static Cast
2020-07-01 16:40:20 +02:00
9d658a1970
Merge pull request #2136 from zachjs/master
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Allow constant function calls in for loops and generate if and case
2020-06-30 17:38:49 +02:00
561890c4e8
Update verific API version check
2020-06-30 12:13:13 +02:00
27cec16cda
Allow constant function calls in for loops and generate if and case
2020-06-29 16:06:17 -06:00
b822beb1b2
Fix crash in verific frontend
2020-06-26 20:11:01 +02:00
6f9be939bd
Parse macro call attached semicolon as empty expression
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-26 15:38:20 +02:00
7cb56f34b0
Fix integer signing grammar
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This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:
parameter integer signed i = 0;
parameter integer unsigned i = 0;
Example of incorrect parameters:
parameter signed integer i = 0;
parameter unsigned integer i = 0;
Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:35:56 +02:00
12c016ebdc
Merge pull request #2188 from antmicro/missing-operators
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Add logic-assignments operators
2020-06-26 07:30:27 +00:00
d6bdc09422
Merge pull request #2189 from antmicro/optional-labels
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Add support for optional labels
2020-06-26 07:29:24 +00:00
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
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Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
539087f417
Support missing sub-assign and and-assign operators
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-25 13:29:06 +02:00
4aec50a863
optimization, all items should have same attributes
2020-06-25 09:18:53 +02:00
a4b4c22c96
Support missing xor-assign operator
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 14:32:12 +02:00
a8750b496e
Support optional labels at the end of package definition
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 11:57:45 +02:00
3b81a1b809
Support optional labels at the end of module definition
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Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
2020-06-24 11:57:45 +02:00
22408f24c7
Add plus-assignment operator
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:54:30 +02:00
416a66aee8
Add or-assignment operator
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-24 11:53:50 +02:00
f993d18755
verific - import attributes for net buses as well
2020-06-24 11:01:06 +02:00
429d37ff41
static cast: simplify
2020-06-19 19:09:43 -07:00
185bbbe681
static cast: support changing size and signedness
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Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)
Fix #535
2020-06-19 17:39:20 -07:00
118e4caa37
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
504f220619
MSVC does not understand __builtin_unreachable
2020-06-17 15:10:08 +02:00
35008e6d40
MSVC cannot omit operand in conditional
2020-06-17 15:10:08 +02:00
b2a0f49371
Merge pull request #2131 from YosysHQ/claire/preserveffs
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Do not optimize away FFs in "prep" and Verific front-end
2020-06-10 12:44:23 +02:00
d6bec3ba1c
verific - detect missing memory to prevent crash.
2020-06-10 11:27:44 +02:00
5c426d2bff
Merge pull request #2112 from YosysHQ/claire/fix2040
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Add latch detection for use_case_method in part-select write
2020-06-09 18:27:59 +02:00
3c7122c378
Do not optimize away FFs in "prep" and Verific fron-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 15:54:14 +02:00
f80b09fc58
Support 2D packed bit arrays in struct/union.
2020-06-09 13:52:09 +01:00
01ec681373
Support 2D bit arrays in structures. Optimise array indexing.
2020-06-08 20:34:52 +01:00
76c499db71
Support packed arrays in struct/union.
2020-06-07 18:33:11 +01:00
7ad0c49905
Add latch detection for use_case_method in part-select write, fixes #2040
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-04 23:25:59 +02:00
352731df4e
Merge pull request #2041 from PeterCrozier/struct
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Implementation of SV structs.
2020-06-04 18:26:07 +02:00
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
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abc9: -dff improvements
2020-06-04 08:15:25 -07:00
3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
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Preserve 'signed'-ness of a verilog wire through RTLIL
2020-06-04 11:23:06 +00:00
0d3f7ea011
Merge branch 'master' into struct
2020-06-03 17:19:28 +01:00
71072d1945
Support asymmetric memories for verific frontend
2020-06-01 10:30:03 +02:00
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic
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ast/simplify: don't bitblast async ROMs declared as `logic`
2020-05-29 16:52:11 +02:00
626c74adbd
Merge pull request #2097 from whitequark/ilang_lexer-fix-erange
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ilang_lexer: fix check for out of range literal
2020-05-29 09:04:27 +00:00
13b2963ded
ilang_lexer: fix check for out of range literal.
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Commit ca70a104
2020-05-29 06:58:44 +00:00
2116d9500c
Merge pull request #2033 from boqwxp/cleanup-verilog-lexer
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verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-29 06:46:33 +00:00
6aa0f72ae9
Silence spurious warning in Verilog lexer when compiling with GCC
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The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.
2020-05-26 17:54:57 +01:00
1ebf7155a7
aiger: cleanup
2020-05-25 08:43:33 -07:00
c5a9abba11
verilog: move attr from simple_behav_stmt to its children to attach
2020-05-25 07:36:53 -07:00
1c117ac023
verilog: do not warn for attributes on null statements
2020-05-25 07:36:53 -07:00
88bddb37c9
verilog: handle empty generate statement by removing gen_stmt_or_null...
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... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
2020-05-25 07:36:53 -07:00
d21a07c7b5
verilog: fix #2037 by permitting (and freeing) attributes on null stmt
2020-05-25 07:36:53 -07:00
574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr
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verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
2020-05-21 11:00:36 -07:00
38e858af8d
Update frontends/verilog/verilog_parser.y
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Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-05-21 09:10:56 -07:00
aee439360b
Add force_downto and force_upto wire attributes.
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Fixes #2058 .
2020-05-19 01:42:40 +02:00
2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
fa8cb3e35d
Revert "Add support for non-power-of-two mem chunks in verific importer"
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This reverts commit 173aa27ca5
2020-05-17 11:31:11 +02:00
39fa1e160d
verific: rewrite initial assume/asserts prior to elaboration
2020-05-15 14:05:28 -07:00
7101ef550b
verilog: attributes before task enable (but 13 s/r conflicts)
2020-05-14 16:10:11 -07:00
4017cc6380
aiger: -xaiger to return $_FF_ flops
2020-05-14 10:33:56 -07:00
6f4f795953
aiger/xaiger: use odd for negedge clk, even for posedge
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Since abc9 doesn't like negative mergeability values
2020-05-14 10:33:56 -07:00
483a190c1b
aiger: -xaiger to parse initial state back into (* init *) on Q wire
2020-05-14 10:33:56 -07:00
53fc3ed645
aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created
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according to mergeability class, and init state as cell attr
2020-05-14 10:33:56 -07:00
5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042
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verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
f02e20907e
Merge pull request #2052 from YosysHQ/claire/verific_memfix
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Add support for non-power-of-two mem chunks in verific importer
2020-05-14 18:45:13 +02:00
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
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ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
173aa27ca5
Add support for non-power-of-two mem chunks in verific importer
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-14 14:38:13 +02:00
237962debd
verilog: default to input in sv mode if task/func has no dir ...
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otherwise error
2020-05-13 13:33:37 -07:00
17f050d3c6
Allow structs within structs.
2020-05-12 17:20:34 +01:00
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
1f3003be7d
verilog: error out when non-ANSI task/func arguments
2020-05-11 13:00:36 -07:00
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs
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Avoid switch fall-through warnings
2020-05-08 05:30:32 +00:00
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
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C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
323aa1df75
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-06 07:22:17 +00:00
283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
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frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-05 07:59:40 -07:00
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
66d0ed2bcc
ast/simplify: don't bitblast async ROMs declared as `logic`.
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Fixes #2020 .
2020-05-05 04:16:59 +00:00
e936ac61ea
ast: swap range regardless of range_left >= 0
2020-05-04 12:18:20 -07:00
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
eca9fc01a7
verilog: set src attribute for primitives
2020-05-04 10:22:05 -07:00
584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations
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frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-04 08:58:50 -07:00
a0afa1787e
aiger: fixes for ports that have start_offset != 0
2020-05-02 10:00:32 -07:00
88185f8959
Fix handling of signed indices in bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbde241942
Merge pull request #2001 from whitequark/wasi
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Add WASI platform support
2020-05-01 21:28:20 +00:00
d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837
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Clear current_scope when done with RTLIL generation
2020-05-01 14:58:41 +02:00
b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-01 07:17:27 +00:00
b43c282e4e
Add WASI platform support.
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This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
5017ff4a97
verific: ignore anonymous enums
2020-04-30 07:48:47 -07:00
97bfe65d3a
verific: support VHDL enums too
2020-04-27 15:17:13 -07:00
adb483ddfd
frontends/json/jsonparse.cc: Like the upto field read_json can also read the signedness of a wire
2020-04-27 10:36:18 -07:00
5f9cd2e2f6
Preserve 'signed'-ness of a verilog wire through RTLIL
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As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987 , now:
RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
dd5f206d9e
verific: recover wiretype/enum attr as part of import_attributes()
2020-04-27 08:43:54 -07:00
b52eccef3a
Revert "verific: import enum attributes from verific"
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This reverts commit 5028e17f7d
2020-04-24 11:57:55 -07:00
d3555c667c
verific: do not assert if wire not found; warn instead
2020-04-23 16:28:11 -07:00
5028e17f7d
verific: import enum attributes from verific
2020-04-22 17:26:56 -07:00
9f1fb11b1d
Clear current_scope when done with RTLIL generation, fixes #1837
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-22 14:51:20 +02:00
06a344efcb
ilang, ast: Store parameter order and default value information.
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Fixes #1819 , #1820 .
2020-04-21 19:09:00 +02:00
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite
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Improved rewrite code for writing to bit slice
2020-04-21 18:46:52 +02:00
abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name
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ast, rpc: record original name of $paramod\* as \hdlname attribute
2020-04-21 01:43:20 +00:00
35990b95ec
Extend support for format strings in Verilog front-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-18 14:08:51 +02:00
41421f5dca
ast, rpc: record original name of $paramod\* as \hdlname attribute.
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The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.
This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
2020-04-18 03:47:28 +00:00
00d74f0b9c
Set Verilog source location for explicit blocks (`begin` ... `end`).
2020-04-17 06:23:03 +00:00
10a814f978
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
2020-04-17 06:16:59 +00:00
9253497358
Add location information to `AST_CONSTANT` nodes.
2020-04-16 19:11:47 +00:00
e86ba3b94d
Make mask-and-shift the default for bitselwrite
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:52 +02:00
e1fb12a4b9
Add LookaheadRewriter for proper bitselwrite support
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:07 +02:00
4d02505820
ast: Fix handling of identifiers in the global scope
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
4711fea6c0
Improved rewrite code for writing to bit slice (disabled for now)
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This adds the new rewrite rule. But it's still missing a check that makes
sure the new rewrite rule is actually a valid substitute in the always
block being processed. Therefore the new rewrite rule is just disabled
for now.
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-15 17:44:37 +02:00
2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum
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ast/simplify: improve enum handling
2020-04-15 14:16:50 +00:00
2106f78bb1
ast/simplify: improve enum handling.
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Before this commit, enum values were serialized as attributes of form
\enum_<width>_<value>
where <value> was a decimal signed integer.
This has multiple drawbacks:
* Enums with large values would be hard to process for downstream
tooling that cannot parse arbitrary precision decimals. (In fact
Yosys also did not correctly process enums with large values,
and would overflow `int`.)
* Enum value attributes were not confined to their own namespace,
making it harder for downstream tooling to enumerate all such
attributes, as opposed to looking up any specific value.
* Enum values could not include x or z, which are explicitly
permitted in the SystemVerilog standard.
After this commit, enum values are serialized as attributes of form
\enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
9b4dab397e
Fix 5bba9c3, closes #1876
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-14 21:05:07 +02:00
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
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support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
0e1beb6f30
Merge pull request #1880 from jjj11x/duplicate_enum
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duplicated enum item names should result in an error
2020-04-14 12:39:28 +00:00
5448f9c85d
Merge pull request #1910 from boqwxp/cleanup_ilang_parser
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Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 08:40:45 +00:00
8a84674a42
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 04:22:00 +00:00
0a178de1b3
verilog: Fix write to deleted object
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-12 18:49:09 +01:00
f1d9ca1563
Merge pull request #1875 from whitequark/read_ilang-int_overflow
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Improve handling of integer literals in RTLIL frontend
2020-04-09 04:02:57 +00:00
c15040c218
aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 12:50:31 -07:00
dbfd6b7530
duplicated enum item names should result in an error
2020-04-07 02:30:11 -04:00
249876b614
support using previously declared types/localparams/params in package
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(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
b494d4c656
read_ilang: improve style. NFC.
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Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-04-06 18:31:15 +00:00
d22888ce74
read_ilang: improve error message for overly long wires.
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Fixes #1838 .
2020-04-06 10:33:02 +00:00
ca70a1049f
read_ilang: detect overflow of integer literals.
2020-04-06 10:32:02 +00:00
cf716e1fff
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice
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ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-02 12:27:10 -07:00
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings
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IdString: use more ID::*, make them easier to use, speed up IdString::in()
2020-04-02 11:47:25 -07:00
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
c69f4b246a
Merge pull request #1846 from dh73/ast_fe
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Adding error message for when size (width) of number literal is zero
2020-04-02 18:15:15 +02:00
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
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kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
f3405e7c79
Merge pull request #1844 from YosysHQ/dave/gen-source-loc
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verilog: Add location info for generate constructs
2020-04-01 20:55:24 +01:00
c3997c77a5
verilog: Add location info for generate constructs
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-01 18:47:20 +01:00
c22fb76664
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-01 09:59:23 -07:00
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
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ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
5132f4099b
ast: simplify to fully populate dynamic slicing case transformation
2020-03-31 11:52:14 -07:00
c859bcf71b
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
92809bb1d3
Adding error message for when size (width) of number literal is zero
2020-03-30 17:18:13 -06:00
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup
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Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-30 13:06:10 -07:00
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 18:14:32 +00:00
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
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Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines
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Add support for SystemVerilog-style `define to Verilog frontend
2020-03-30 13:51:12 +02:00
1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit
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ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
2020-03-27 17:28:26 +01:00
f8c065ed1c
Inline productions to follow house style.
2020-03-27 16:21:45 +00:00
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
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This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
6040593994
Revert over-aggressive change to a more modest cleanup.
2020-03-27 09:46:40 +00:00
9a8a644ad1
Error duplicate declarations of a typedef name in the same scope.
2020-03-24 14:35:21 +00:00
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
6cad865d12
Simplify was not being called for packages. Broke typedef enums.
2020-03-22 18:20:46 -07:00
c06eda2504
Build pkg_user_types before parsing in case of changes in the design.
2020-03-22 18:20:46 -07:00
0aaa36ca6d
Clear pkg_user_types if no packages following a 'design -reset-vlog'.
2020-03-22 18:20:46 -07:00
14f32028ec
Parser changes to support typedef.
2020-03-22 18:20:46 -07:00
f828cb5132
Merge pull request #1788 from YosysHQ/eddie/fix_ndebug
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Fix NDEBUG warnings
2020-03-19 14:58:06 -07:00
d46259becd
Merge pull request #1787 from YosysHQ/mmicko/lexer_deps
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Add dependency to verilog_lexer.cc
2020-03-19 18:24:40 +01:00
dc75ed7dac
Add one mode dependency
2020-03-19 16:53:40 +01:00
43092f063f
Fix NDEBUG warnings
2020-03-19 08:48:39 -07:00
b473264a06
Merge pull request #1775 from huaixv/asserts_locations
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Add precise locations for asserts
2020-03-19 13:12:18 +01:00
eb30d66d01
Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-19 07:29:00 +00:00
cd82ccd258
Add precise locations for asserts
2020-03-19 10:22:07 +08:00
4555b5b819
kernel: more pass by const ref, more speedups
2020-03-18 11:21:53 -07:00
6dd2024965
Add AST node source location information in a couple more parser rules.
2020-03-17 06:22:12 +00:00
569e834df2
Merge pull request #1759 from zeldin/constant_with_comment_redux
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refixed parsing of constant with comment between size and value
2020-03-14 13:34:59 +02:00
faf4ee69de
Merge pull request #1754 from boqwxp/precise_locations
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Set AST node source location in more parser rules.
2020-03-14 11:18:39 +02:00
5e94bf0291
refixed parsing of constant with comment between size and value
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The three parts of a based constant (size, base, digits) are now three
separate tokens, allowing the linear whitespace (including comments)
between them to be treated as normal inter-token whitespace.
2020-03-11 18:21:44 +01:00
7b679eecb3
Fix compilation for emcc
2020-03-11 22:09:24 +08:00
2d63bf5877
verilog: also set location for simple_behavioral_stmt
2020-03-10 10:29:24 -07:00
da8270aa01
Set AST source locations in more parser rules.
2020-03-10 01:50:39 +00:00
a7cc4673c3
Fix partsel expr bit width handling and add test case
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-08 16:12:12 +01:00
d59da5a4e4
Fix bison warning for "pure-parser" option
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-03 08:41:55 -08:00
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
91892465e1
Merge pull request #1681 from YosysHQ/eddie/fix1663
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verilog: instead of modifying localparam size, extend init constant expr
2020-03-03 08:34:31 -08:00
4f889b2f57
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
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abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
2020-03-02 12:32:27 -08:00
5bba9c3640
ast: fixes #1710 ; do not generate RTLIL for unreachable ternary
2020-02-27 16:55:55 -08:00
825b96fdcf
Comment out log()
2020-02-27 16:53:49 -08:00
e79376d6cb
ast: quiet down when deriving blackbox modules
2020-02-27 10:17:29 -08:00
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
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Improve specify parser
2020-02-21 09:15:17 -08:00
cd044a2bb6
Merge pull request #1642 from jjj11x/jjj11x/sv-enum
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Enum support
2020-02-20 18:17:25 +01:00
ea4bd161b6
verilog: add support for more delays than just rise/fall
2020-02-19 11:09:37 -08:00
a31ba8e5d5
remove unnecessary blank line
2020-02-17 04:42:49 -05:00
d12ba42a74
add attributes for enumerated values in ilang
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- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
2020-02-17 04:42:42 -05:00
6320f2692b
separate out enum_item/param implementation when they should be different
2020-02-17 04:42:30 -05:00
d20c1dac73
verilog: ignore ranges too without -specify
2020-02-13 17:58:43 -08:00
6b58c1820c
verilog: improve specify support when not in -specify mode
2020-02-13 13:27:15 -08:00
2e51dc1856
verilog: ignore '&&&' when not in -specify mode
2020-02-13 13:06:13 -08:00
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
7cfdf4ffa7
verilog: fix $specify3 check
2020-02-13 12:42:04 -08:00
e069259a53
Merge pull request #1679 from thasti/delay-parsing
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Fix crash on wire declaration with delay
2020-02-13 12:01:27 +01:00
c34d7b13f4
ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
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Before this commit, every initial assignment to a memory generated
two wires and four assigns in a process. For unknown reasons (I did
not investigate), large amounts of assigns cause quadratic slowdown
later in the AST frontend, in processAst/removeSignalFromCaseTree.
As a consequence, common and reasonable Verilog code, such as:
reg [`WIDTH:0] mem [0:`DEPTH];
integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0;
took extremely long time to be processed; around 80 s for a 8-wide,
8192-deep memory.
After this commit, initial assignments where address and/or data are
constant (after `generate`) do not incur the cost of intermediate
wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant.
This results in speedups of orders of magnitude for common memory
sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep
memory, and only 5.8 s to process a 8-wide, 131072-deep one.
As a bonus, this change also results in nontrivial speedups later
in the synthesis pipeline, since pass sequencing issues meant that
all of these intermediate wires were subject to transformations such
as width reduction, even though they existed solely to be constant
folded away in `memory_collect`.
2020-02-07 00:41:54 +00:00
da485dc007
Modified $readmem[hb] to use '\' or '/' according the OS
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Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-06 10:10:29 -03:00
fc33287bc1
verilog: instead of modifying localparam size, extend init constant expr
2020-02-05 17:19:42 -08:00
b844b078db
correct wire declaration grammar for #1614
2020-02-03 21:29:40 +01:00
313a425bd5
Merge branch 'master' of https://github.com/YosysHQ/yosys
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Solved a conflict into the CHANGELOG
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:56:41 -03:00
71f3afb9a2
Replaced strlen by GetSize into simplify.cc
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As recommended in CodingReadme.
Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
2020-02-03 10:44:09 -03:00
4bfd2ef4f3
sv: Improve handling of wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
5df591c023
hierarchy: Resolve SV wildcard port connections
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
50f86c11b2
sv: Add lexing and parsing of .* (wildcard port conns)
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Signed-off-by: David Shah <dave@ds0.me>
2020-02-02 16:12:33 +00:00
9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf
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ast: Add support for $sformatf system function
2020-02-02 14:53:46 +00:00
b4c30cfc8d
Fixed a bug in the new feature of $readmem[hb] when an empty string is provided
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-02-01 17:03:56 -03:00
d74b9604e3
Modified the new search for files of $readmem[hb] to be backward compatible
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 22:10:51 -03:00
7b3fe404ab
$readmem[hb] file inclusion is now relative to the Verilog file
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Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
2020-01-31 18:20:22 -03:00
2ce7a0d369
Merge pull request #1667 from YosysHQ/clifford/verificnand
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Add Verific support for OPER_REDUCE_NAND
2020-01-30 19:55:53 +01:00
60876ce183
Merge pull request #1503 from YosysHQ/eddie/verific_help
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`verific` pass to print help message when command syntax error
2020-01-30 18:05:16 +01:00
ffadaddab5
Merge pull request #1654 from YosysHQ/eddie/sby_fix69
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verific: unflatten struct ports
2020-01-30 18:03:35 +01:00
23c44afaed
Add Verific support for OPER_REDUCE_NAND
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-30 18:01:13 +01:00
6d27d43727
Add and use SigSpec::reverse()
2020-01-28 10:37:16 -08:00
ce6a690d27
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
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Now done in read_aiger
2020-01-27 13:30:27 -08:00
f443695a38
Merge remote-tracking branch 'origin/master' into eddie/verific_help
2020-01-27 10:34:10 -08:00
d730bba6d2
verific: no help() when no YOSYS_ENABLE_VERIFIC
2020-01-27 10:32:18 -08:00
7b445121cc
verific: also unflatten for 'hierarchy' flow as per @cliffordwolf
2020-01-27 10:15:22 -08:00
c7fbe13db5
read_aiger: set abc9_box_seq attr
2020-01-24 13:11:43 -08:00
cccc0ae112
verific: unflatten struct ports
2020-01-24 10:12:52 -08:00
73526a6f10
read_aiger: also parse abc9_mergeability
2020-01-22 14:21:25 -08:00
cd093c00f8
read_aiger: discard LUT inputs with nodeID == 0; not < 2
2020-01-21 11:56:30 -08:00
7f728bc116
read_aiger: ignore constant inputs on LUTs
2020-01-21 11:16:50 -08:00
22c967e35e
ast: Add support for $sformatf system function
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Signed-off-by: David Shah <dave@ds0.me>
2020-01-19 21:20:17 +00:00
98c6bd7630
fix bug introduced by not taking all of PeterCrozier's changes in 16ea4ea6
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The if(str == node->str) is in fact necessary (otherwise causes generate
for in Multiplier_2D in tests/simple/multiplier.v to fail with error
message "Right hand side of 3rd expression of generate for-loop is not
constant!"). Note: in PeterCrozier's implementation, the break only
breaks out of the switch-case, not the outer for loop.
2020-01-17 02:07:42 -05:00
549deb6373
fix enum in generate blocks
2020-01-16 18:13:30 -05:00
41a0a93dcc
allow enums to be declared at toplevel scope
2020-01-16 18:13:14 -05:00
cc2236d0c0
lexer doesn't seem to return TOK_REG for logic anymore
2020-01-16 18:08:58 -05:00
5ddf84d430
allow enum typedefs
2020-01-16 17:17:42 -05:00
16ea4ea61a
partial rebase of PeterCrozier's enum work onto current master
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I tried to keep only the enum-related changes, and minimize the diff. (The
original commit also had a lot of work done to get typedefs working, but yosys
has diverged quite a bit since the 2018-03-09 commit, with a new typedef
implementation.) I did not include the import related changes either.
Original commit:
"Initial implementation of enum, typedef, import. Still a WIP."
881833aa73
2020-01-16 13:51:47 -05:00
03ce2c72bb
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-15 16:42:16 -08:00
05c8858a90
read_aiger: $lut prefix in front
2020-01-15 14:31:32 -08:00
53a99ade9c
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-14 11:46:56 -08:00
f63f76c372
read_aiger: also rename "$0"
2020-01-14 09:01:53 -08:00
2c65e1abac
abc9: break SCC by setting (* keep *) on output wires
2020-01-13 21:45:27 -08:00
ee95fa959a
read_aiger: uniquify wires with $aiger<autoidx> prefix
2020-01-13 21:28:27 -08:00
766e16b525
read_aiger: make $and/$not/$lut the prefix not suffix
2020-01-13 17:34:37 -08:00
d979648b7a
read_aiger: more accurate debug message
2020-01-09 10:02:19 -08:00
943ea4bf9e
read_aiger: do not double-count outputs for flops
2020-01-09 08:55:36 -08:00
2ca8c10e7a
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-07 15:43:22 -08:00
2ac36031d4
read_aiger: consistency between ascii and binary; also name latches
2020-01-07 13:30:31 -08:00
8f5388ea5b
read_aiger fixes
2020-01-07 11:59:57 -08:00
b94cf0c126
read_aiger: connect identical signals together
2020-01-07 11:43:28 -08:00
baba33fbd3
read_aiger: cope with latches and POs with same name
2020-01-07 11:22:48 -08:00
738af17a26
read_aiger: default -clk_name to be empty
2020-01-07 11:21:45 -08:00
61a2a60595
read_aiger: do not process box connections, work standalone
2020-01-07 09:48:11 -08:00
b57f692a9e
read_aiger: consistency between ascii and binary
2020-01-07 09:32:34 -08:00
83616e7866
read_aiger: add -xaiger option
2020-01-06 12:43:29 -08:00
96db05aaef
parse_xaiger to not take box_lookup
2019-12-31 17:06:03 -08:00
e5ed8e8e21
parse_xaiger to reorder ports too
2019-12-31 16:50:22 -08:00
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531
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verilog: preserve size of $genval$-s in for loops
2019-12-19 12:21:33 -05:00
22dd9f107c
Send people to symbioticeda.com instead of verific.com
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-12-18 13:06:34 +01:00
a6fdb9f5c1
aiger frontend to user shorter, $-prefixed, names
2019-12-17 15:50:01 -08:00
5f50e4f112
Cleanup xaiger, remove unnecessary complexity with inout
2019-12-17 15:45:26 -08:00
0875a07871
read_xaiger to cope with optional '\n' after 'c'
2019-12-17 15:45:26 -08:00
c0339bbbf1
Name inputs/outputs of aiger 'i%d' and 'o%d'
2019-12-13 16:21:09 -08:00
e9dc2759c4
Fixed some missing "verilog_" in documentation
2019-12-13 10:17:05 -03:00
1ac1697e15
Stray log_dump
2019-12-11 16:59:00 -08:00
af36943cb9
Preserve size of $genval$-s in for loops
2019-12-11 16:52:37 -08:00
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
ab667d3d47
Call abc9 with "&write -n", and parse_xaiger() to cope
2019-12-06 16:35:57 -08:00
69d8c1386a
Do not connect undriven POs to 1'bx
2019-12-06 16:21:06 -08:00
7dece7955e
Merge pull request #1551 from whitequark/manual-cell-operands
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Clarify semantics of comb cells, in particular shifts
2019-12-05 08:24:24 -08:00
e97e33d00d
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
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Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
0ce22cea46
read_ilang: do bounds checking on bit indices
2019-11-27 22:24:39 +01:00
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
db323685a4
Add Verific support for SVA nexttime properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 16:11:56 +01:00
e93e4a7a2c
Improve handling of verific primitives in "verific -import -V" mode
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 16:00:07 +01:00
6af0d03fae
Add Verific SVA support for "always" properties
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 15:52:21 +01:00
9e4801cca7
sv: Correct parsing of always_comb, always_ff and always_latch
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 20:27:19 +00:00
a576747483
Consistent log message, ignore 's' extension
2019-11-20 15:40:46 -08:00
55bda2b2c6
Correctly treat empty modules as blackboxes in Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-20 12:56:31 +01:00
f6ff311a1d
Do not rename VHDL entities to "entity(impl)" when they are top modules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-20 12:54:10 +01:00
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
e2819ce31c
Oops
2019-11-19 13:25:38 -08:00
84711f0e8c
Print help message for verific pass
2019-11-19 13:24:48 -08:00
65f197e28f
Add check for valid macro names in macro definitions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-07 13:30:03 +01:00
84982b3083
Improve naming scheme for (VHDL) modules imported from Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 12:13:50 +02:00
d49c6b2cba
Add "verific -L"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 09:14:03 +02:00
5025aab8c9
Add "verilog_defines -list" and "verilog_defines -reset"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 13:35:56 +02:00
4033ff8c2e
Fix handling of "restrict" in Verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 12:39:28 +02:00
71936209cf
Fix parsing of .cname BLIF statements
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 09:06:57 +02:00
935d3e19e2
Add .blackbox support to blif front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 00:00:27 +02:00
e84cedfae4
Use "(id)" instead of "id" for types as temporary hack
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-14 05:24:31 +02:00
304e5f9ea4
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 13:03:06 -07:00
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
whitequark
Zachary Snow
Michael Singer
Marcelina Kościelnicka
TimRudy
Karol Gugala
Claire Xen
Miodrag Milanovic
Kamil Rakoczy
Diego H
Henner Zeller
David Shah
Lukasz Dalek
Tom Verbeure
georgerennie
Julius Roob
Claire Xenia Wolf
Udi Finkelstein
Kazuki Sakamoto
Anonymous Maarten
Peter Crozier
Eddie Hung
Rupert Swarbrick
Claire Wolf
Xiretza
Alberto Gonzalez
Vamsi K Vytla
Jeff Wang
Diego H
N. Engelhardt
Rupert Swarbrick
huaixv
Marcus Comstedt
jiegec
Rodrigo Alejandro Melo
Stefan Biereigel
Rodrigo Alejandro Melo
Marcin Kościelnicki