riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

verilog: handle empty generate statement by removing gen_stmt_or_null... 

... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.
This commit is contained in:
Eddie Hung 2020-05-11 10:20:33 -07:00
parent d21a07c7b5
commit 88bddb37c9
1 changed files with 8 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
frontends/verilog/verilog_parser.y
View File

@ -2440,7 +2440,7 @@ gen_case_item:
} case_select {
case_type_stack.push_back(0);
SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
} gen_stmt_or_null {
} gen_stmt_block {
case_type_stack.pop_back();
ast_stack.pop_back();
};
@ -2532,7 +2532,11 @@ module_gen_body:
/* empty */;
gen_stmt_or_module_body_stmt:
gen_stmt | module_body_stmt;
gen_stmt | module_body_stmt |
attr ';' {
log_file_warning(current_filename, get_line_num(), "Attribute(s) attached to null statement. Ignoring.\n");
free_attr($1);
};
// this production creates the obligatory if-else shift/reduce conflict
gen_stmt:
@ -2554,7 +2558,7 @@ gen_stmt:
AstNode *block = new AstNode(AST_GENBLOCK);
ast_stack.back()->children.push_back(block);
ast_stack.push_back(block);
} gen_stmt_or_null {
} gen_stmt_block {
ast_stack.pop_back();
} opt_gen_else {
SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
@ -2604,11 +2608,8 @@ gen_stmt_block:
ast_stack.pop_back();
};
gen_stmt_or_null:
gen_stmt_block | ';';
opt_gen_else:
TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN;
expr:
basic_expr {