mirror of https://github.com/YosysHQ/yosys.git
ast, rpc: record original name of $paramod\* as \hdlname attribute.
The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
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parent
115fc261e6
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41421f5dca
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@ -306,17 +306,8 @@ struct FirrtlWorker
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// If this is a parameterized module, its parent module is encoded in the cell type
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if (cell->type.begins_with("$paramod"))
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{
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std::string::iterator it;
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for (it = cell_type.begin(); it < cell_type.end(); it++)
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{
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switch (*it) {
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case '\\': /* FALL_THROUGH */
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case '=': /* FALL_THROUGH */
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case '\'': /* FALL_THROUGH */
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case '$': instanceOf.append("_"); break;
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default: instanceOf.append(1, *it); break;
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}
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}
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log_assert(cell->has_attribute(ID::hdlname));
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instanceOf = cell->get_string_attribute(ID::hdlname);
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}
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else
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{
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@ -1565,6 +1565,9 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
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rewritten.reserve(GetSize(parameters));
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AstNode *new_ast = ast->clone();
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if (!new_ast->attributes.count(ID::hdlname))
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new_ast->attributes[ID::hdlname] = AstNode::mkconst_str(stripped_name);
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para_counter = 0;
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for (auto child : new_ast->children) {
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if (child->type != AST_PARAMETER)
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@ -217,6 +217,8 @@ struct RpcModule : RTLIL::Module {
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module.second->name = mangled_name;
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module.second->design = design;
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module.second->attributes.erase(ID::top);
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if (!module.second->has_attribute(ID::hdlname))
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module.second->set_string_attribute(ID::hdlname, module.first.str());
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design->modules_[mangled_name] = module.second;
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derived_design->modules_.erase(module.first);
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}
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