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Set Verilog source location for explicit blocks (`begin` ... `end`).

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Alberto Gonzalez 2020-04-17 06:23:03 +00:00
parent 10a814f978
commit 00d74f0b9c
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frontends/verilog/verilog_parser.y
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@ -2246,6 +2246,7 @@ behavioral_stmt:
exitTypeScope();
if ($4 != NULL && $8 != NULL && *$4 != *$8)
frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1);
SET_AST_NODE_LOC(ast_stack.back(), @2, @8);
delete $4;
delete $8;
ast_stack.pop_back();