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Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.

This commit is contained in:
Alberto Gonzalez 2020-04-17 06:16:59 +00:00
parent c69db910ac
commit 10a814f978
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frontends/verilog/verilog_parser.y
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@ -1924,11 +1924,13 @@ always_events:
always_event:
TOK_POSEDGE expr {
AstNode *node = new AstNode(AST_POSEDGE);
SET_AST_NODE_LOC(node, @1, @1);
ast_stack.back()->children.push_back(node);
node->children.push_back($2);
} |
TOK_NEGEDGE expr {
AstNode *node = new AstNode(AST_NEGEDGE);
SET_AST_NODE_LOC(node, @1, @1);
ast_stack.back()->children.push_back(node);
node->children.push_back($2);
} |