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lexer doesn't seem to return TOK_REG for logic anymore

This commit is contained in:
Jeff Wang 2020-01-16 17:11:08 -05:00 committed by Jeff Wang
parent 5ddf84d430
commit cc2236d0c0
1 changed files with 4 additions and 3 deletions
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7
frontends/verilog/verilog_parser.y
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@ -1261,13 +1261,14 @@ enum_type: TOK_ENUM {
enum_base_type: int_vec param_range
| int_atom
| /* nothing */ { addRange(astbuf1); }
| /* nothing */ {astbuf1->is_reg = true; addRange(astbuf1); }
;
int_atom: TOK_INTEGER { addRange(astbuf1); } // probably should do byte, range [7:0] here
int_atom: TOK_INTEGER {astbuf1->is_reg=true; addRange(astbuf1); } // probably should do byte, range [7:0] here
;
int_vec: TOK_REG { astbuf1->is_reg = true; } // lexer returns this for logic|bit too
int_vec: TOK_REG {astbuf1->is_reg = true;}
| TOK_LOGIC {astbuf1->is_logic = true;}
;
enum_name_list: