riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

allow enum typedefs

This commit is contained in:
Jeff Wang 2020-01-16 17:17:42 -05:00 committed by Jeff Wang
parent 16ea4ea61a
commit 5ddf84d430
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
frontends/verilog/verilog_parser.y
View File

@ -1523,7 +1523,12 @@ typedef_decl:
ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1));
ast_stack.back()->children.back()->str = *$4;
};
} |
TOK_TYPEDEF enum_type TOK_ID ';' {
ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1));
ast_stack.back()->children.back()->str = *$3;
}
;
cell_stmt:
attr TOK_ID {