riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix R/R conflicts 

This commit fixes R/R conflicts introduced by commit 7e83a51.
Parameter logic is already defined as part of `param_range_type` rule.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
This commit is contained in:
Kamil Rakoczy 2020-07-10 10:14:31 +02:00
parent de649b9194
commit 0ffaddee5e
1 changed files with 1 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
frontends/verilog/verilog_parser.y
View File

@ -1348,13 +1348,6 @@ param_real:
astbuf1->children.push_back(new AstNode(AST_REALVALUE));
}
param_logic:
TOK_LOGIC {
// SV LRM 6.11, Table 6-8: logic -- 4-state, user-defined vector size, unsigned
astbuf1->is_signed = false;
astbuf1->is_logic = true;
}
param_range:
range {
if ($1 != NULL) {
@ -1366,10 +1359,8 @@ param_integer_type: param_integer param_signed
param_range_type: type_vec param_signed param_range
param_implicit_type: param_signed param_range
param_integer_vector_type: param_logic param_signed param_range
param_type:
param_integer_type | param_integer_vector_type | param_real | param_range_type | param_implicit_type |
param_integer_type | param_real | param_range_type | param_implicit_type |
hierarchical_type_id {
astbuf1->is_custom_type = true;
astbuf1->children.push_back(new AstNode(AST_WIRETYPE));