mirror of https://github.com/YosysHQ/yosys.git
Add and use SigSpec::reverse()
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@ -410,7 +410,7 @@ void AigerReader::parse_xaiger()
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RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID));
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log_assert(output_sig);
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uint32_t nodeID;
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std::vector<SigBit> input_bits;
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RTLIL::SigSpec input_sig;
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for (unsigned j = 0; j < cutLeavesM; ++j) {
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nodeID = parse_xaiger_literal(f);
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log_debug2("\t%u\n", nodeID);
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@ -420,10 +420,10 @@ void AigerReader::parse_xaiger()
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}
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RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
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log_assert(wire);
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input_bits.push_back(wire);
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input_sig.append(wire);
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}
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// Reverse input order as fastest input is returned first
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RTLIL::SigSpec input_sig(std::vector<SigBit>(input_bits.rbegin(), input_bits.rend()));
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input_sig.reverse();
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// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
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ce.clear();
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ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
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@ -851,6 +851,8 @@ public:
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RTLIL::SigSpec repeat(int num) const;
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void reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }
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bool operator <(const RTLIL::SigSpec &other) const;
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bool operator ==(const RTLIL::SigSpec &other) const;
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inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }
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