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Add and use SigSpec::reverse()

This commit is contained in:
Eddie Hung 2020-01-28 10:37:16 -08:00
parent e18aeda7ed
commit 6d27d43727
2 changed files with 5 additions and 3 deletions
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6
frontends/aiger/aigerparse.cc
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@ -410,7 +410,7 @@ void AigerReader::parse_xaiger()
RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID));
log_assert(output_sig);
uint32_t nodeID;
std::vector<SigBit> input_bits;
RTLIL::SigSpec input_sig;
for (unsigned j = 0; j < cutLeavesM; ++j) {
nodeID = parse_xaiger_literal(f);
log_debug2("\t%u\n", nodeID);
@ -420,10 +420,10 @@ void AigerReader::parse_xaiger()
}
RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
log_assert(wire);
input_bits.push_back(wire);
input_sig.append(wire);
}
// Reverse input order as fastest input is returned first
RTLIL::SigSpec input_sig(std::vector<SigBit>(input_bits.rbegin(), input_bits.rend()));
input_sig.reverse();
// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
ce.clear();
ce.compute_deps(output_sig, input_sig.to_sigbit_pool());

2
kernel/rtlil.h
View File

@ -851,6 +851,8 @@ public:
RTLIL::SigSpec repeat(int num) const;
void reverse() { inline_unpack(); std::reverse(bits_.begin(), bits_.end()); }
bool operator <(const RTLIL::SigSpec &other) const;
bool operator ==(const RTLIL::SigSpec &other) const;
inline bool operator !=(const RTLIL::SigSpec &other) const { return !(*this == other); }