mirror of https://github.com/YosysHQ/yosys.git
sv: Add lexing and parsing of .* (wildcard port conns)
Signed-off-by: David Shah <dave@ds0.me>
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@ -431,6 +431,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
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"+:" { return TOK_POS_INDEXED; }
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"-:" { return TOK_NEG_INDEXED; }
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".*" { return TOK_AUTOCONNECT_ALL; }
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[-+]?[=*]> {
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if (!specify_mode) REJECT;
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frontend_verilog_yylval.string = new std::string(yytext);
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@ -138,7 +138,7 @@ struct specify_rise_fall {
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%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
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%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
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%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
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%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR
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%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_AUTOCONNECT_ALL
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%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
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%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
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%token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
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@ -1580,6 +1580,9 @@ cell_port:
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node->children.back()->str = *$3;
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delete $3;
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free_attr($1);
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} |
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attr TOK_AUTOCONNECT_ALL {
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astbuf2->attributes[ID(autoconnect)] = AstNode::mkconst_int(1, false);
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};
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always_comb_or_latch:
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