mirror of https://github.com/YosysHQ/yosys.git
Do not connect undriven POs to 1'bx
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@ -1005,15 +1005,10 @@ void AigerReader::post_process()
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if (other_wire) {
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other_wire->port_input = false;
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other_wire->port_output = false;
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}
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if (wire->port_input) {
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if (other_wire)
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if (wire->port_input)
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module->connect(other_wire, SigSpec(wire, i));
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}
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else {
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// Since we skip POs that are connected to Sx,
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// re-connect them here
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module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
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else
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module->connect(SigSpec(wire, i), other_wire);
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}
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}
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}
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