riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

verilog: set src attribute for primitives

This commit is contained in:
Eddie Hung 2020-05-04 10:22:05 -07:00
parent ad8e7878f6
commit eca9fc01a7
2 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
frontends/ast/simplify.cc
View File

@ -1739,8 +1739,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
AstNode *node = children_list[1];
if (op_type != AST_POS)
for (size_t i = 2; i < children_list.size(); i++)
for (size_t i = 2; i < children_list.size(); i++) {
node = new AstNode(op_type, node, children_list[i]);
node->location = location;
}
if (invert_results)
node = new AstNode(AST_BIT_NOT, node);

4
frontends/verilog/verilog_parser.y
View File

@ -1747,7 +1747,9 @@ single_prim:
/* no name */ {
astbuf2 = astbuf1->clone();
ast_stack.back()->children.push_back(astbuf2);
} '(' cell_port_list ')';
} '(' cell_port_list ')' {
SET_AST_NODE_LOC(astbuf2, @1, @$);
}
cell_parameter_list_opt:
'#' '(' cell_parameter_list ')' | /* empty */;