mirror of https://github.com/YosysHQ/yosys.git
ast: quiet down when deriving blackbox modules
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88d5997c80
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e79376d6cb
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@ -939,14 +939,15 @@ RTLIL::Const AstNode::realAsConst(int width)
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}
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// create a new AstModule from an AST_MODULE AST node
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static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL)
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static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false)
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{
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log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
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if (defer)
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log("Storing AST representation for module `%s'.\n", ast->str.c_str());
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else
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else if (!quiet) {
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log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
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}
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current_module = new AstModule;
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current_module->ast = NULL;
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@ -1484,14 +1485,16 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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// create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
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RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool /*mayfail*/)
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{
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bool quiet = lib || attributes.count(ID(blackbox)) || attributes.count(ID(whitebox));
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AstNode *new_ast = NULL;
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std::string modname = derive_common(design, parameters, &new_ast);
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std::string modname = derive_common(design, parameters, &new_ast, quiet);
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if (!design->has(modname)) {
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new_ast->str = modname;
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design->add(process_module(new_ast, false));
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design->add(process_module(new_ast, false, NULL, quiet));
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design->module(modname)->check();
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} else {
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} else if (!quiet) {
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log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
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}
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@ -1500,7 +1503,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
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}
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// create a new parametric module (when needed) and return the name of the generated module
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std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out)
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std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool quiet)
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{
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std::string stripped_name = name.str();
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@ -1516,13 +1519,15 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
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para_counter++;
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std::string para_id = child->str;
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if (parameters.count(para_id) > 0) {
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log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
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if (!quiet)
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log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
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para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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continue;
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}
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para_id = stringf("$%d", para_counter);
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if (parameters.count(para_id) > 0) {
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log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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if (!quiet)
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log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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continue;
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}
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@ -1539,7 +1544,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
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if (design->has(modname))
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return modname;
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log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
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if (!quiet)
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log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
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loadconfig();
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AstNode *new_ast = ast->clone();
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@ -1550,12 +1556,14 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
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para_counter++;
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std::string para_id = child->str;
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if (parameters.count(para_id) > 0) {
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log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
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if (!quiet)
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log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
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goto rewrite_parameter;
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}
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para_id = stringf("$%d", para_counter);
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if (parameters.count(para_id) > 0) {
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log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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if (!quiet)
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log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
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goto rewrite_parameter;
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}
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continue;
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@ -307,7 +307,7 @@ namespace AST
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~AstModule() YS_OVERRIDE;
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RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
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RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE;
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std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out);
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std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool quiet = false);
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void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
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RTLIL::Module *clone() const YS_OVERRIDE;
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void loadconfig() const;
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