Fix SYNTHESIS always being defined in Verilog frontend

frontends/verilog/preproc.cc

@@ -321,7 +321,6 @@ struct define_body_t
 define_map_t::define_map_t()
 {
 	add("YOSYS", "1");
-	add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
 }
 
 // We must define this destructor here (rather than relying on the default), because we need to

frontends/verilog/verilog_frontend.cc

@@ -446,6 +446,9 @@ struct VerilogFrontend : public Frontend {
 			}
 			break;
 		}
+
+		defines_map.add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
+
 		extra_args(f, filename, args, argidx);
 
 		log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());