mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
frontend: cleanup to use more ID::*, more dict<> instead of map<>
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commit
283b1130a6
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@ -171,7 +171,7 @@ struct AST_INTERNAL::LookaheadRewriter
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for (auto c : node->id2ast->children)
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wire->children.push_back(c->clone());
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wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++);
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wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
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wire->is_logic = true;
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while (wire->simplify(true, false, false, 1, -1, false, false)) { }
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current_ast_mod->children.push_back(wire);
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@ -920,11 +920,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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range_swapped = templ->range_swapped;
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range_left = templ->range_left;
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range_right = templ->range_right;
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attributes["\\wiretype"] = mkconst_str(resolved_type->str);
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attributes[ID::wiretype] = mkconst_str(resolved_type->str);
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//check if enum
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if (templ->attributes.count("\\enum_type")){
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if (templ->attributes.count(ID::enum_type)){
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//get reference to enum node:
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std::string enum_type = templ->attributes["\\enum_type"]->str.c_str();
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const std::string &enum_type = templ->attributes[ID::enum_type]->str;
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// log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type));
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// log("current scope:\n");
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// for (auto &it : current_scope)
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@ -972,7 +972,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed);
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enum_item_str.append(val.as_string());
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//set attribute for available val to enum item name mappings
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attributes[enum_item_str.c_str()] = mkconst_str(enum_item->str);
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attributes[enum_item_str] = mkconst_str(enum_item->str);
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}
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}
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@ -1021,7 +1021,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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range_swapped = templ->range_swapped;
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range_left = templ->range_left;
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range_right = templ->range_right;
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attributes["\\wiretype"] = mkconst_str(resolved_type->str);
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attributes[ID::wiretype] = mkconst_str(resolved_type->str);
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for (auto template_child : templ->children)
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children.push_back(template_child->clone());
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did_something = true;
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@ -1812,14 +1812,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
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wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
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wire_mask->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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wire_mask->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
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wire_mask->is_logic = true;
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while (wire_mask->simplify(true, false, false, 1, -1, false, false)) { }
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current_ast_mod->children.push_back(wire_mask);
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AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
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wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
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wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
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wire_data->is_logic = true;
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while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
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current_ast_mod->children.push_back(wire_data);
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@ -2639,7 +2639,7 @@ skip_dynamic_range_lvalue_expansion:;
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bool recommend_const_eval = false;
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bool require_const_eval = in_param ? false : has_const_only_constructs(recommend_const_eval);
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if ((in_param || recommend_const_eval || require_const_eval) && !decl->attributes.count("\\via_celltype"))
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if ((in_param || recommend_const_eval || require_const_eval) && !decl->attributes.count(ID::via_celltype))
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{
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bool all_args_const = true;
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for (auto child : children) {
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@ -2698,9 +2698,9 @@ skip_dynamic_range_lvalue_expansion:;
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goto replace_fcall_with_id;
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}
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if (decl->attributes.count("\\via_celltype"))
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if (decl->attributes.count(ID::via_celltype))
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{
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std::string celltype = decl->attributes.at("\\via_celltype")->asAttrConst().decode_string();
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std::string celltype = decl->attributes.at(ID::via_celltype)->asAttrConst().decode_string();
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std::string outport = str;
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if (celltype.find(' ') != std::string::npos) {
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@ -2794,7 +2794,7 @@ skip_dynamic_range_lvalue_expansion:;
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wire->is_reg = true;
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wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
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if (child->type == AST_ENUM_ITEM)
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wire->attributes["\\enum_base_type"] = child->attributes["\\enum_base_type"];
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wire->attributes[ID::enum_base_type] = child->attributes[ID::enum_base_type];
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wire_cache[child->str] = wire;
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@ -4094,7 +4094,7 @@ void AstNode::allocateDefaultEnumValues()
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int last_enum_int = -1;
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for (auto node : children) {
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log_assert(node->type==AST_ENUM_ITEM);
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node->attributes["\\enum_base_type"] = mkconst_str(str);
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node->attributes[ID::enum_base_type] = mkconst_str(str);
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for (size_t i = 0; i < node->children.size(); i++) {
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switch (node->children[i]->type) {
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case AST_NONE:
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@ -107,16 +107,16 @@ module:
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delete_current_module = false;
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if (current_design->has($2)) {
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RTLIL::Module *existing_mod = current_design->module($2);
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if (!flag_overwrite && (flag_lib || (attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()))) {
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if (!flag_overwrite && (flag_lib || (attrbuf.count(ID::blackbox) && attrbuf.at(ID::blackbox).as_bool()))) {
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log("Ignoring blackbox re-definition of module %s.\n", $2);
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delete_current_module = true;
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} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
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} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
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rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
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} else if (flag_nooverwrite) {
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log("Ignoring re-definition of module %s.\n", $2);
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delete_current_module = true;
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} else {
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log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", $2);
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log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", $2);
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current_design->remove(existing_mod);
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}
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}
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@ -48,7 +48,7 @@ static void error_on_dpi_function(AST::AstNode *node)
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error_on_dpi_function(child);
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}
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static void add_package_types(std::map<std::string, AST::AstNode *> &user_types, std::vector<AST::AstNode *> &package_list)
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static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std::vector<AST::AstNode *> &package_list)
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{
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// prime the parser's user type lookup table with the package qualified names
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// of typedefed names in the packages seen so far.
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@ -50,7 +50,7 @@ namespace VERILOG_FRONTEND
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extern std::vector<UserTypeMap *> user_type_stack;
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// names of package typedef'ed types
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extern std::map<std::string, AST::AstNode*> pkg_user_types;
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extern dict<std::string, AST::AstNode*> pkg_user_types;
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// state of `default_nettype
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extern bool default_nettype_wire;
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@ -50,12 +50,12 @@ using namespace VERILOG_FRONTEND;
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YOSYS_NAMESPACE_BEGIN
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namespace VERILOG_FRONTEND {
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int port_counter;
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std::map<std::string, int> port_stubs;
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std::map<std::string, AstNode*> *attr_list, default_attr_list;
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std::stack<std::map<std::string, AstNode*> *> attr_list_stack;
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std::map<std::string, AstNode*> *albuf;
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dict<std::string, int> port_stubs;
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dict<IdString, AstNode*> *attr_list, default_attr_list;
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std::stack<dict<IdString, AstNode*> *> attr_list_stack;
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dict<IdString, AstNode*> *albuf;
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std::vector<UserTypeMap*> user_type_stack;
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std::map<std::string, AstNode*> pkg_user_types;
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dict<std::string, AstNode*> pkg_user_types;
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std::vector<AstNode*> ast_stack;
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struct AstNode *astbuf1, *astbuf2, *astbuf3;
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struct AstNode *current_function_or_task;
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@ -87,7 +87,7 @@ YOSYS_NAMESPACE_END
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int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
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static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
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static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
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{
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for (auto &it : *al) {
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if (ast->attributes.count(it.first) > 0)
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@ -97,7 +97,7 @@ static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
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delete al;
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}
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static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
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static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
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{
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for (auto &it : *al) {
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if (ast->attributes.count(it.first) > 0)
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@ -106,7 +106,7 @@ static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
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}
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}
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static void free_attr(std::map<std::string, AstNode*> *al)
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static void free_attr(dict<IdString, AstNode*> *al)
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{
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for (auto &it : *al)
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delete it.second;
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@ -192,7 +192,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
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%union {
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std::string *string;
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struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
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std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
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YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
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struct specify_target *specify_target_ptr;
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struct specify_triple *specify_triple_ptr;
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struct specify_rise_fall *specify_rise_fall_ptr;
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@ -289,7 +289,7 @@ attr:
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{
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if (attr_list != nullptr)
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attr_list_stack.push(attr_list);
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attr_list = new std::map<std::string, AstNode*>;
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attr_list = new dict<IdString, AstNode*>;
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for (auto &it : default_attr_list)
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(*attr_list)[it.first] = it.second->clone();
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} attr_opt {
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@ -311,7 +311,7 @@ defattr:
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DEFATTR_BEGIN {
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if (attr_list != nullptr)
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attr_list_stack.push(attr_list);
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attr_list = new std::map<std::string, AstNode*>;
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attr_list = new dict<IdString, AstNode*>;
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for (auto &it : default_attr_list)
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delete it.second;
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default_attr_list.clear();
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@ -1390,7 +1390,7 @@ enum_type: TOK_ENUM {
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delete astbuf1;
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astbuf1 = tnode;
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tnode->type = AST_WIRE;
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tnode->attributes["\\enum_type"] = AstNode::mkconst_str(astbuf2->str);
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tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
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// drop constant but keep any range
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delete tnode->children[0];
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tnode->children.erase(tnode->children.begin()); }
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@ -2345,7 +2345,7 @@ unique_case_attr:
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case_attr:
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attr unique_case_attr {
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if ($2) (*$1)["\\parallel_case"] = AstNode::mkconst_int(1, false);
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if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
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$$ = $1;
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};
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@ -74,6 +74,8 @@ X(EN)
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X(EN_DST)
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X(EN_POLARITY)
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X(EN_SRC)
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X(enum_base_type)
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X(enum_type)
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X(equiv_merged)
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X(equiv_region)
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X(extract_order)
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@ -196,6 +198,7 @@ X(U)
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X(unique)
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X(unused_bits)
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X(V)
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X(via_celltype)
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X(wand)
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X(whitebox)
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X(WIDTH)
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