mirror of https://github.com/YosysHQ/yosys.git
read_aiger: add -xaiger option
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b70e87137d
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83616e7866
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@ -1000,18 +1000,21 @@ struct AigerFrontend : public Frontend {
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log("Load module from an AIGER file into the current design.\n");
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log("\n");
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log(" -module_name <module_name>\n");
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log(" Name of module to be created (default: <filename>)\n");
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log(" name of module to be created (default: <filename>)\n");
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log("\n");
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log(" -clk_name <wire_name>\n");
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log(" If specified, AIGER latches to be transformed into $_DFF_P_ cells\n");
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log(" clocked by wire of this name. Otherwise, $_FF_ cells will be used.\n");
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log(" if specified, AIGER latches to be transformed into $_DFF_P_ cells\n");
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log(" clocked by wire of this name. otherwise, $_FF_ cells will be used\n");
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log("\n");
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log(" -map <filename>\n");
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log(" read file with port and latch symbols\n");
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log("\n");
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log(" -wideports\n");
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log(" Merge ports that match the pattern 'name[int]' into a single\n");
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log(" multi-bit port 'name'.\n");
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log(" merge ports that match the pattern 'name[int]' into a single\n");
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log(" multi-bit port 'name'\n");
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log("\n");
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log(" -xaiger\n");
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log(" read XAIGER extensions\n");
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log("\n");
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -1021,7 +1024,7 @@ struct AigerFrontend : public Frontend {
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RTLIL::IdString clk_name = "\\clk";
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RTLIL::IdString module_name;
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std::string map_filename;
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bool wideports = false;
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bool wideports = false, xaiger = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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@ -1042,6 +1045,10 @@ struct AigerFrontend : public Frontend {
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wideports = true;
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continue;
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}
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if (arg == "-xaiger") {
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xaiger = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx, true);
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@ -1061,7 +1068,10 @@ struct AigerFrontend : public Frontend {
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}
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AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
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reader.parse_aiger();
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if (xaiger)
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reader.parse_xaiger();
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else
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reader.parse_aiger();
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}
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} AigerFrontend;
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