mirror of https://github.com/YosysHQ/yosys.git
aiger: cleanup
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9e6c288e5a
commit
1ebf7155a7
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@ -775,7 +775,6 @@ void AigerReader::post_process()
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}
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}
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dict<int, Wire*> mergeability_to_clock;
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for (uint32_t i = 0; i < flopNum; i++) {
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RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
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log_assert(d);
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@ -895,7 +894,9 @@ void AigerReader::post_process()
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}
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else if (type == "box") {
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RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
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if (cell) // ABC could have optimised this box away
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if (!cell)
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log_debug("Box %d (%s) no longer exists.\n", variable, log_id(escaped_s));
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else
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module->rename(cell, escaped_s);
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}
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else
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@ -907,6 +908,8 @@ void AigerReader::post_process()
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auto name = wp.first;
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int min = wp.second.first;
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int max = wp.second.second;
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if (min == 0 && max == 0)
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continue;
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RTLIL::Wire *wire = module->wire(name);
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if (wire)
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