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Merge pull request #1918 from whitequark/simplify-improve_enum
ast/simplify: improve enum handling
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commit
2d436bc4f1
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@ -443,8 +443,8 @@ Verilog Attributes and non-standard features
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- The ``wiretype`` attribute is added by the verilog parser for wires of a
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typedef'd type to indicate the type identifier.
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- Various ``enum_{width}_{value}`` attributes are added to wires of an
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enumerated type to give a map of possible enum items to their values.
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- Various ``enum_value_{value}`` attributes are added to wires of an enumerated type
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to give a map of possible enum items to their values.
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- The ``enum_base_type`` attribute is added to enum items to indicate which
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enum they belong to (enums -- anonymous and otherwise -- are
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@ -931,9 +931,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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);
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}
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//start building attribute string
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std::string enum_item_str = "\\enum_";
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enum_item_str.append(std::to_string(width));
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enum_item_str.append("_");
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std::string enum_item_str = "\\enum_value_";
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//get enum item value
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if(enum_item->children[0]->type != AST_CONSTANT){
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log_error("expected const, got %s for %s (%s)\n",
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@ -941,8 +939,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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enum_item->str.c_str(), enum_node->str.c_str()
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);
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}
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int val = enum_item->children[0]->asInt(is_signed);
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enum_item_str.append(std::to_string(val));
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RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed);
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enum_item_str.append(val.as_string());
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//set attribute for available val to enum item name mappings
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attributes[enum_item_str.c_str()] = mkconst_str(enum_item->str);
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}
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