Alberto Gonzalez
5accf08ef9
Skip reading stdout from the solver that if it isn't a line reading only "sat", "unsat", or "unknown".
2020-03-26 01:21:01 +00:00
Sahand Kashani
6c2b220af5
Remove use of auto for simple types + simplify src attribute computation
2020-03-24 21:07:08 +01:00
Claire Wolf
c9555c9ade
Revert part of 0fda8308
from #1746 that broke other smtbmc flows
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-24 17:33:46 +01:00
Sahand Kashani
018116e478
Refactor to directly call ILANG_BACKEND::dump_const() + directly lookup src attribute
2020-03-24 10:55:21 +01:00
Teguh Hofstee
b08932cb81
fix typo in `write_smt2` help
2020-03-23 02:14:26 -07:00
Sahand Kashani
f48fb26c0f
Indentation conventions
2020-03-23 09:01:17 +01:00
Sahand Kashani-Akhavan
566e08485a
Const parameter in function (backends/firrtl/firrtl.cc)
...
Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-03-23 08:56:28 +01:00
Sahand Kashani
21492914a2
Strip quotes around fileinfo strings
...
Yosys puts quotes around the string that represents the fileinfo whereas
firrtl does not. So when firrtl sees quotes, it escapes them with an extra
backslash which makes it hard to read afterwards.
2020-03-21 15:57:53 +01:00
Sahand Kashani
c0b2a9af2e
Add fileinfo to firrtl backend for assignments and non-instance cells
2020-03-21 12:54:23 +01:00
Sahand Kashani
3e04e29dec
Refactor fileinfo emission characters to single location
2020-03-20 18:31:12 +01:00
Sahand Kashani
ed9f8bfe6e
Add fileinfo to firrtl backend for instances
2020-03-19 16:24:18 +01:00
Sahand Kashani
59236314f8
Add fileinfo to firrtl backend for modules and wires
2020-03-19 14:59:05 +01:00
Sahand Kashani
bdce9c28c2
Add fileinfo to firrtl backend for top-level circuit
2020-03-19 00:14:27 +01:00
N. Engelhardt
020f6d167a
Merge pull request #1768 from boqwxp/smt2_cleanup
...
Clean up pseudo-private member usage in `backends/smt2/smt2.cc`.
2020-03-16 13:49:10 +01:00
N. Engelhardt
a2e340de43
Merge pull request #1746 from boqwxp/optimization
...
Add support for optimizing exists-forall problems.
2020-03-16 12:23:14 +01:00
Claire Wolf
bf018b184d
Improve write_btor symbol handling
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-14 15:49:43 +01:00
Alberto Gonzalez
07f0874779
Clean up pseudo-private member usage in `backends/smt2/smt2.cc`.
2020-03-13 21:49:12 +00:00
Alberto Gonzalez
0fda8308bc
Add support for optimizing exists-forall problems.
...
Modifies smt2 backend to recognize `$anyconst` etc. assigned to a wire with the `maximize` or `minimize` attribute and emit `; yosys-smt2-maximize` or `; yosys-smt2-minimize` directives as appropriate.
Modifies `backends/smt2/smtbmc.py` and `smtio.py` to recognize those directives and emit a `(maximize ...)` or `(minimize ...)` command at the end of `smt_forall_assert()`, as described in the paper "νZ - An Optimizing SMT Solver" by Nikolaj Bjørner et al.
Adds an example `examples/smtbmc/demo9.v` to show how it can be used.
2020-03-13 17:10:29 +00:00
Miodrag Milanovic
746629f18d
remove include where not used
2020-03-13 14:55:53 +01:00
Claire Wolf
29e2b2dc05
Add info-file and cover features to write_btor
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-13 13:46:32 +01:00
Eddie Hung
3be7784d0e
xaiger: remove some unnecessary operations ...
...
... since they can not be triggered by (* keep *) anymore
(but could still be triggered by (* abc9_scc *) !?!)
2020-03-06 10:51:47 -08:00
Eddie Hung
91a7a74ac4
abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling
2020-03-06 10:20:30 -08:00
Eddie Hung
6bb3d9f9c0
Make TimingInfo::TimingInfo(SigBit) constructor explicit
2020-02-27 10:17:29 -08:00
Eddie Hung
5ff60d2057
write_xaiger: add comment about arrival times of flop outputs
2020-02-27 10:17:29 -08:00
Eddie Hung
1ef1ca812b
Get rid of (* abc9_{arrival,required} *) entirely
2020-02-27 10:17:29 -08:00
Eddie Hung
e22fee6cdd
abc9_ops: ignore (* abc9_flop *) if not '-dff'
2020-02-27 10:17:29 -08:00
Eddie Hung
12d70ca8fb
xilinx: improve specify functionality
2020-02-27 10:17:29 -08:00
Eddie Hung
760096e8d2
Merge pull request #1703 from YosysHQ/eddie/specify_improve
...
Improve specify parser
2020-02-21 09:15:17 -08:00
Eddie Hung
f9f86fd758
Revert "abc9: fix abc9_arrival for flops"
...
This reverts commit f7c0dbecee
.
2020-02-14 16:08:04 -08:00
Eddie Hung
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
Eddie Hung
f5cc8cfa79
write_xaiger: default value for abc9_init
2020-02-13 12:37:17 -08:00
Eddie Hung
f7c0dbecee
abc9: fix abc9_arrival for flops
2020-02-13 12:34:09 -08:00
R. Ou
20ce4118da
json: Change compat mode to directly emit ints <= 32 bits
...
This increases compatibility with certain older parsers in some cases
that worked before commit 15fae357
but do not work with the current
compat-int mode
2020-02-09 01:01:18 -08:00
whitequark
6f67dd8df5
Merge pull request #1683 from whitequark/write_verilog-memattrs
...
write_verilog: dump $mem cell attributes
2020-02-07 02:54:04 +00:00
Marcin Kościelnicki
8f559b070a
edif: more resilience to mismatched port connection sizes.
...
Fixes #1653 .
2020-02-06 18:45:03 +01:00
whitequark
e95a8ba763
write_verilog: dump $mem cell attributes.
...
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
2020-02-06 16:22:42 +00:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required
...
abc9: add support for required times
2020-02-05 18:59:40 +01:00
Marcin Kościelnicki
00fba62711
json: remove the 32-bit parameter special case
...
Before, the rules for encoding parameters in JSON were as follows:
- if the parameter is not a string:
- if it is exactly 32 bits long and there are no z or x bits, emit it
as an int
- otherwise, emit it as a string made of 0/1/x/z characters
- if the parameter is a string:
- if it contains only 0/1/x/z characters, append a space at the end
to distinguish it from a non-string
- otherwise, emit it directly
However, this caused a problem in the json11 parser used in nextpnr:
yosys emits unsigned ints, and nextpnr parses them as signed, using
the value of INT_MIN for values that overflow the signed int range.
This caused destruction of LUT5 initialization values. Since both
nextpnr and yosys parser can also accept 32-bit parameters in the
same encoding as other widths, let's just remove that special case.
The old behavior is still left behind a `-compat-int` flag, in case
someone relies on it.
2020-02-01 16:16:26 +01:00
Claire Wolf
50d70288d0
Preserve wires with keep attribute in EDIF back-end
...
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-29 14:07:11 +01:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
...
Refactor `abc9` pass
2020-01-27 13:29:15 -08:00
Eddie Hung
f2576c096c
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
2020-01-27 12:29:28 -08:00
Claire Wolf
485f31f681
Improve yosys-smtbmc "solver not found" handling
...
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 17:48:56 +01:00
Eddie Hung
3d9737c1bd
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-21 16:27:40 -08:00
Eddie Hung
cd8f55a911
write_xaiger: fix for (* keep *) on flop output
2020-01-21 09:43:04 -08:00
Claire Wolf
30642e9570
Merge pull request #1629 from YosysHQ/mwk/edif-z
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edif: Just ignore connections to 'z
2020-01-21 18:35:15 +01:00
Eddie Hung
38aa248385
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-15 11:26:11 -08:00
Eddie Hung
d6da9c0c0f
write_xaiger: skip abc9_flop only if abc_box_seq present
2020-01-15 11:25:20 -08:00
Eddie Hung
485e08e436
abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)
2020-01-14 16:33:41 -08:00
Eddie Hung
48984a7605
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-14 16:32:46 -08:00
Eddie Hung
1c41dc6b95
write_xaiger: do not export flop inputs as POs
2020-01-14 16:17:27 -08:00
Eddie Hung
0e4285ca0d
abc9_ops: generate flop box ids, add abc9_required to FD* cells
2020-01-14 15:05:49 -08:00
Eddie Hung
588a713b54
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-14 14:28:07 -08:00
Eddie Hung
4656f202c6
abc9_ops: -reintegrate to not trim box padding anymore
2020-01-14 14:27:29 -08:00
Eddie Hung
aaafd784a5
write_xaiger: skip if no arrival times
2020-01-14 13:05:39 -08:00
Eddie Hung
915e7dde73
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-14 12:57:56 -08:00
Eddie Hung
654247abe9
abc9_ops/write_xaiger: update doc
2020-01-14 12:40:36 -08:00
Eddie Hung
468386d67d
abc9_ops: -prep_holes -> -prep_xaiger, move padding to write_xaiger
2020-01-14 12:25:45 -08:00
Eddie Hung
53a99ade9c
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-14 11:46:56 -08:00
Miodrag Milanović
9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr
...
Export wire properties in EDIF
2020-01-14 19:19:32 +01:00
Eddie Hung
eb7dd7d374
write_xaiger: fix case of PI and CI and (* keep *)
2020-01-13 23:23:21 -08:00
Eddie Hung
2c65e1abac
abc9: break SCC by setting (* keep *) on output wires
2020-01-13 21:45:27 -08:00
Eddie Hung
a6d4ea7463
abc9: respect (* keep *) on cells
2020-01-13 19:21:11 -08:00
Eddie Hung
9ec948f396
write_xaiger: add support and test for (* keep *) on wires
2020-01-13 19:07:55 -08:00
Eddie Hung
0d2c06ee47
write_xaiger: cache arrival times
2020-01-13 09:50:50 -08:00
Marcin Kościelnicki
55f86eda36
edif: Just ignore connections to 'z
...
Connecting a const 'z to a net should be equivalent to not connecting it
at all, so let's just ignore such connections on output.
2020-01-13 14:49:31 +01:00
Eddie Hung
f9aae90e7a
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
2020-01-12 15:19:41 -08:00
Eddie Hung
295e241c07
cleanup
2020-01-11 17:28:24 -08:00
Eddie Hung
79db12f238
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-11 17:26:25 -08:00
Eddie Hung
58ab9f6021
write_xaiger: create holes_sigmap before modifications
2020-01-11 17:25:32 -08:00
Eddie Hung
1ccee4b95e
write_xaiger: sort holes by offset as well as port_id
2020-01-11 11:49:57 -08:00
Eddie Hung
f24de88f38
log_debug() for abc9_{arrival,required} times
2020-01-10 17:13:27 -08:00
Miodrag Milanovic
6888799c75
remove whitespace
2020-01-10 12:38:03 +01:00
Miodrag Milanovic
2bcd55f1ae
Export wire properties as well in EDIF
2020-01-10 12:33:58 +01:00
Eddie Hung
ceabd5bc39
write_xaiger: cleanup
2020-01-09 14:03:43 -08:00
Eddie Hung
3177437224
write_xaiger: cope with abc9_arrival as string of ints
2020-01-09 10:05:03 -08:00
Eddie Hung
7532416cd7
write_xaiger: cleanup holes generation
2020-01-08 18:27:09 -08:00
Eddie Hung
5f7349f26d
write_xaiger: holes PIs only if whitebox
2020-01-08 15:40:37 -08:00
Eddie Hung
8d0cc654a4
Stray log_module
2020-01-06 15:14:38 -08:00
Eddie Hung
aa58472a29
Revert "write_xaiger to pad, not abc9_ops -prep_holes"
...
This reverts commit b5f60e055d
.
2020-01-06 13:34:45 -08:00
Eddie Hung
921ff0f5e3
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-06 12:04:08 -08:00
Eddie Hung
886c5c5883
write_xaiger: make more robust, update doc
2020-01-06 10:23:04 -08:00
Eddie Hung
19ec54f956
write_aiger: make more robust
2020-01-06 10:18:59 -08:00
Eddie Hung
b5f60e055d
write_xaiger to pad, not abc9_ops -prep_holes
2020-01-05 10:20:24 -08:00
Eddie Hung
6556a1347a
Fix when -dff not given
2020-01-04 09:17:01 -08:00
Eddie Hung
930f03e883
Call -prep_holes before aigmap; fix topo ordering
2020-01-03 15:38:18 -08:00
Eddie Hung
a819656972
WIP
2020-01-03 14:59:55 -08:00
Eddie Hung
559f3379e8
Preserve topo ordering from -prep_holes to write_xaiger
2020-01-03 14:37:58 -08:00
Eddie Hung
bb70915fb8
WIP
2020-01-03 13:21:56 -08:00
Eddie Hung
e1f494ab1d
WIP
2020-01-03 13:08:52 -08:00
Eddie Hung
e62eb02c1d
Restore write_xaiger's holes_mode since port_id order causes QoR
...
regressions inside abc9
2020-01-03 12:32:05 -08:00
Eddie Hung
dedea5a58d
Cleanup
2020-01-02 17:25:14 -08:00
Eddie Hung
c28bea0382
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-02 15:57:35 -08:00
Eddie Hung
07feedfa73
write_xaiger: get rid of external_bits dict
2020-01-02 15:32:58 -08:00
Eddie Hung
8e507bd807
abc9 -keepff -> -dff; refactor dff operations
2020-01-02 12:36:54 -08:00
Eddie Hung
11577b46fc
Get rid of (* abc9_keep *) in write_xaiger too
2020-01-01 08:38:23 -08:00
Eddie Hung
ac808c5e2a
attributes.count() -> get_bool_attribute()
2020-01-01 08:33:32 -08:00
Eddie Hung
96db05aaef
parse_xaiger to not take box_lookup
2019-12-31 17:06:03 -08:00
Eddie Hung
cac7f5d82e
Do not re-order carry chain ports, just precompute iteration order
2019-12-31 16:12:40 -08:00
Eddie Hung
134e70e8e7
write_xaiger: be more precise with ff_bits, remove ff_aig_map
2019-12-31 10:21:11 -08:00
Eddie Hung
3798fa3bea
Retry getting rid of write_xaiger's holes_mode
2019-12-31 09:59:17 -08:00
Eddie Hung
436c96e2fb
Revert "Get rid of holes_mode"
...
This reverts commit 7997e2a90f
.
2019-12-30 23:29:14 -08:00
Eddie Hung
7997e2a90f
Get rid of holes_mode
2019-12-30 20:15:09 -08:00
Eddie Hung
b42b64e8ed
Move Pass::call() out of abc9_ops into abc9
2019-12-30 19:23:54 -08:00
Eddie Hung
88334cab89
Cleanup
2019-12-30 18:49:33 -08:00
Eddie Hung
65baefecd3
Rid unnecessary if
2019-12-30 18:26:35 -08:00
Eddie Hung
e2bbe33a88
Get rid of holes_mode
2019-12-30 18:24:29 -08:00
Eddie Hung
b50de28c04
Add abc9_ops -prep_holes
2019-12-30 18:00:49 -08:00
Eddie Hung
0735572934
write_xaiger to use scratchpad for stats; cleanup abc9
2019-12-30 15:35:33 -08:00
Eddie Hung
d1fccd5a2d
Remove unused
2019-12-30 14:35:52 -08:00
Eddie Hung
3cbbae251f
Call "proc" if processes inside whiteboxes
2019-12-30 14:33:05 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Eddie Hung
d7ada66497
Add "synth_xilinx -dff" option, cleanup abc9
2019-12-30 14:13:16 -08:00
Eddie Hung
237415e78c
write_xaiger: inherit port ordering from original module
2019-12-27 16:44:18 -08:00
Eddie Hung
a56d6970f2
Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"
...
This reverts commit 92654f73ea
, reversing
changes made to 3e14ff1667
.
2019-12-27 16:05:58 -08:00
Eddie Hung
9e6632c40a
Merge branch 'master' of github.com:YosysHQ/yosys
2019-12-27 15:37:26 -08:00
Eddie Hung
3d4644804e
write_xaiger: simplify c{i,o}_bits
2019-12-27 15:37:17 -08:00
David Shah
df31ade3b3
Revert "write_xaiger: only instantiate each whitebox cell type once"
2019-12-27 23:25:20 +00:00
Eddie Hung
dd503a5f3f
Really fix it!
2019-12-27 15:18:55 -08:00
Eddie Hung
49881b4468
write_xaiger: fix arrival times for non boxes
2019-12-27 11:30:18 -08:00
Eddie Hung
6eadd4390a
write_xaiger to opt instead of just clean whiteboxes
2019-12-23 08:35:53 -08:00
Eddie Hung
a75e08c709
write_xaiger: only instantiate each whitebox cell type once
2019-12-20 13:07:24 -08:00
Eddie Hung
10e82e103f
Revert "Optimise write_xaiger"
2019-12-20 12:05:45 -08:00
Eddie Hung
5f50e4f112
Cleanup xaiger, remove unnecessary complexity with inout
2019-12-17 15:45:26 -08:00
Eddie Hung
e82a9bc642
Do not sigmap
2019-12-17 00:03:03 -08:00
Eddie Hung
2e71130700
Revert "Use sigmap signal"
...
This reverts commit 42f990f3a6
.
2019-12-17 00:00:07 -08:00
Eddie Hung
42f990f3a6
Use sigmap signal
2019-12-16 16:49:42 -08:00
Eddie Hung
b19fc8839b
Skip $inout transformation if not a PI
2019-12-16 14:39:13 -08:00
Eddie Hung
78c0246d4a
Revert "write_xaiger: use sigmap bits more consistently"
...
This reverts commit 6c340112fe
.
2019-12-16 14:35:35 -08:00
Eddie Hung
6c340112fe
write_xaiger: use sigmap bits more consistently
2019-12-16 10:21:57 -08:00
Eddie Hung
91467938c4
Stray newline
2019-12-06 17:08:19 -08:00
Eddie Hung
f2ac36de4a
write_xaiger to inst each cell type once, do not call techmap/aigmap
2019-12-06 17:06:10 -08:00
Eddie Hung
1f96de04c9
Fix writing non-whole modules, including inouts and keeps
2019-12-06 16:19:10 -08:00
Eddie Hung
a682a3cf93
write_xaiger to support part-selected modules again
2019-12-05 17:54:43 -08:00
Eddie Hung
c6ee2fb482
Cleanup
2019-12-03 19:21:47 -08:00
Eddie Hung
df52bc80d8
write_xaiger to consume abc9_init attribute for abc9_flops
2019-12-03 18:47:44 -08:00
Eddie Hung
419ca5c207
Revert "Fold loop"
...
This reverts commit a30d5e1cc3
.
2019-11-27 21:55:56 -08:00
Eddie Hung
449b1d2c6f
Add comment, use sigmap
2019-11-27 13:20:12 -08:00
Eddie Hung
403214f44d
Revert "Fold loop"
...
This reverts commit da51492dbc
.
2019-11-27 12:35:25 -08:00
Eddie Hung
5e67df38ed
latch -> box
2019-11-26 22:59:05 -08:00
Eddie Hung
a30d5e1cc3
Fold loop
2019-11-26 21:57:50 -08:00
Eddie Hung
68717dd03b
Do not sigmap keep bits inside write_xaiger
2019-11-26 21:57:50 -08:00
Eddie Hung
7136cee6b4
xaiger: do not promote output wires
2019-11-26 21:55:37 -08:00
Eddie Hung
99702efaba
xaiger: do not promote output wires
2019-11-26 19:03:02 -08:00
Eddie Hung
da51492dbc
Fold loop
2019-11-25 15:43:37 -08:00
Eddie Hung
7f0914a408
Do not sigmap keep bits inside write_xaiger
2019-11-25 15:42:07 -08:00
Eddie Hung
81548d1ef9
write_xaiger back to working with whole modules only
2019-11-22 16:52:17 -08:00
Eddie Hung
8ef241c6f4
Revert "write_xaiger to not use module POs but only write outputs if driven"
...
This reverts commit 0ab1e496dc
.
2019-11-22 13:24:28 -08:00
Eddie Hung
0ab1e496dc
write_xaiger to not use module POs but only write outputs if driven
2019-11-21 16:19:28 -08:00
Eddie Hung
929beda19c
abc9 to support async flops $_DFF_[NP][NP][01]_
2019-11-19 16:57:26 -08:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
whitequark
3c643c57df
write_verilog: add -extmem option, to write split memory init files.
...
Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
2019-11-18 01:27:21 +00:00
Clifford Wolf
cd44826d50
Use cell name for btor bad state props when it is a public name
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-14 11:57:38 +01:00
Makai Mann
d88cc139a0
Add an info string symbol for bad states in btor backend
2019-11-11 16:40:51 -08:00
Clifford Wolf
5110a34dd7
Fix write_aiger bug added in 524af21
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-04 14:25:13 +01:00
Clifford Wolf
81876a3734
Merge pull request #1393 from whitequark/write_verilog-avoid-init
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write_verilog: do not print (*init*) attributes on regs
2019-10-27 10:25:01 +01:00
Clifford Wolf
f02623abb5
Bugfix in smtio vcd handling of $-identifiers
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-23 00:04:34 +02:00
Eddie Hung
b2e34f932a
Rename $currQ to $abc9_currQ
2019-10-07 15:31:43 -07:00
Eddie Hung
90a954bb9c
Get rid of latch_* in write_xaiger
2019-10-07 13:09:13 -07:00
Eddie Hung
1504ca2cd9
Remove "write_xaiger -zinit"
2019-10-07 11:58:49 -07:00
Eddie Hung
e1554b56dd
Add comment on default flop init
2019-10-07 11:56:17 -07:00
Eddie Hung
d9fba95177
Get rid of output_port lookup
2019-10-07 11:49:06 -07:00
Eddie Hung
3879ca1398
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
Eddie Hung
3c6e5d82a6
Error if $currQ not found
2019-10-05 09:06:13 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
549d6ea467
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 10:55:23 -07:00
Clifford Wolf
2ed2e9c3e8
Change smtbmc "Warmup failed" status to "PREUNSAT"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-03 14:59:07 +02:00
Clifford Wolf
a84a2d74c7
Fix btor back-end to use "state" instead of "input" for undef init bits
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-02 12:48:04 +02:00
Eddie Hung
1b96d29174
No need to punch ports at all
2019-09-30 17:02:20 -07:00
Eddie Hung
e529872b01
Remove need for $currQ port connection
2019-09-30 16:33:40 -07:00
Eddie Hung
eecfdda614
Cleanup
2019-09-30 15:24:03 -07:00
Eddie Hung
74678227c7
Use a cell_cache to instantiate once rather than opt_merge call
2019-09-30 13:21:07 -07:00
Eddie Hung
a6994c5f16
scc call on active module module only, plus cleanup
2019-09-30 12:57:19 -07:00
Eddie Hung
bd8356799a
Use derived module
2019-09-30 12:34:28 -07:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
f3e150d9a5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 09:21:51 -07:00
Miodrag Milanović
ce0631c371
Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out
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Support binary files for backends, fixes #1407
2019-09-29 10:37:34 +02:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Miodrag Milanovic
0c380f0855
Add aiger and protobuf backends binary support
2019-09-28 09:51:48 +02:00
Miodrag Milanovic
d0493925ec
Support binary files for backends, fixes #1407
2019-09-28 09:36:18 +02:00
Eddie Hung
cfa6dd61ef
Use abc_mergeability attr for "r" extension
2019-09-27 18:41:43 -07:00
Eddie Hung
dc154c39a8
Fix infinite recursion
2019-09-27 17:45:49 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Aman Goel
5eebfabe42
Corrects btor2 backend
2019-09-27 12:40:17 -04:00
Eddie Hung
44374b1b2b
"abc_padding" attr for blackbox outputs that were padded, remove them later
2019-09-23 21:58:40 -07:00
Eddie Hung
c340fbfab2
Force $inout.out ports to begin with '$' to indicate internal
2019-09-23 21:58:04 -07:00
whitequark
4f426c2ac4
write_verilog: do not print (*init*) attributes on regs.
...
If an init value is emitted for a reg, an (*init*) attribute is never
necessary, since it is exactly equivalent. On the other hand, some
tools that consume Verilog (ISE, Vivado, Quartus) complain about
(*init*) attributes because their interpretation differs from Yosys.
All (*init*) attributes that would not become reg init values anyway
are emitted as before.
2019-09-22 16:52:06 +00:00
Eddie Hung
2d9484c12c
When two boxes connect to each other, need not be a (* keep *)
2019-09-19 15:40:28 -07:00
Clifford Wolf
779ce3537f
Add "write_aiger -L"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-18 13:33:02 +02:00
Clifford Wolf
b88d2e5f30
Fix stupid bug in btor back-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-18 11:56:14 +02:00
Sean Cross
c1b628508d
backends: smt2: use $(CXX) variable for compiler
...
The Makefile assumes the compiler is called `gcc`, which isn't always
true. In fact, if we're building on msys2 or msys2-64, the compiler
is called `i686-w64-mingw32-g++` or `x86_64-w64-mingw32-g++`.
Use the variable instead of hardcoding the name, to fix building on
these systems.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-08 15:47:09 +08:00
Eddie Hung
e9bb252e77
Recognise built-in types (e.g. $_DFF_*)
2019-08-30 20:15:09 -07:00
Eddie Hung
3247442bf9
Revert "Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)""
...
This reverts commit 8f0c1232d7
.
2019-08-28 17:34:00 -07:00
Eddie Hung
082a01954b
Revert "Output "h" extension only if boxes"
...
This reverts commit 399ac760ff
.
2019-08-28 17:30:54 -07:00
Eddie Hung
399ac760ff
Output "h" extension only if boxes
2019-08-21 11:31:18 -07:00
Eddie Hung
8f0c1232d7
Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)"
...
This reverts commit 8182cb9d91
.
2019-08-21 11:29:40 -07:00
Eddie Hung
8182cb9d91
Fix omode which inserts an output if none exists (otherwise abc9 breaks)
2019-08-20 21:30:16 -07:00
Eddie Hung
4d123b7638
Revert "Only xaig if GetSize(output_bits) > 0"
...
This reverts commit 7b646101e9
.
2019-08-20 21:22:38 -07:00
Eddie Hung
7b646101e9
Only xaig if GetSize(output_bits) > 0
2019-08-20 20:57:13 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
...
This reverts commit 091bf4a18b
.
2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
1b5d2de1d4
Do not sigmap!
2019-08-20 15:23:26 -07:00
Eddie Hung
c00d72cdb3
Minor refactor
2019-08-20 14:47:58 -07:00
Eddie Hung
45d4b33f0c
Output i/o/h extensions even if no boxes or flops
2019-08-19 13:17:31 -07:00
Eddie Hung
91687d3fea
Add (* abc_arrival *) attribute
2019-08-19 12:33:24 -07:00
Eddie Hung
2f4e0a5388
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 10:07:27 -07:00
Eddie Hung
10c69f71e9
Use %d
2019-08-19 09:16:20 -07:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
4fe307f1bc
Compute abc_scc_break and move CI/CO outside of each abc9
2019-08-16 15:41:17 -07:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
05c46a31dc
Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell
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FIRRTL error on unsupported cell
2019-08-10 09:47:10 +02:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Jim Lawson
5e8a98c8fd
Merge branch 'master' into firrtl_err_on_unsupported_cell
...
# Conflicts:
# backends/firrtl/firrtl.cc
2019-08-07 10:14:45 -07:00
Eddie Hung
3090da2d98
Run "clean -purge" on holes_module in its own design
2019-08-07 09:54:27 -07:00
Clifford Wolf
48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
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Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
2019-08-07 12:31:32 +02:00
David Shah
dee8f61781
Merge pull request #1241 from YosysHQ/clifford/jsonfix
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Improved JSON attr/param encoding
2019-08-07 10:40:38 +01:00
Eddie Hung
e38f40af5b
Use IdString::begins_with()
2019-08-06 16:42:25 -07:00
Eddie Hung
a6bc9265fb
RTLIL::S{0,1} -> State::S{0,1}
2019-08-06 16:23:37 -07:00
Eddie Hung
046e1a5214
Use State::S{0,1}
2019-08-06 16:22:47 -07:00
Eddie Hung
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Clifford Wolf
0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix
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Visual Studio build fix
2019-08-02 17:07:39 +02:00
Miodrag Milanovic
28b7053a01
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
Clifford Wolf
15fae357f6
Implement improved JSON attr/param encoding
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-01 12:34:52 +02:00
Jim Lawson
3b8c917025
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
...
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
2019-07-31 09:27:38 -07:00
Miodrag Milanovic
35d28de478
Visual Studio build fix
2019-07-31 09:10:24 +02:00
Jim Lawson
7e298084e4
Call log_error() instead of log_warning() on unsupported cell type in FIRRTL backend.
2019-07-24 13:33:16 -07:00
Clifford Wolf
927f0caa9d
Merge pull request #1203 from whitequark/write_verilog-zero-width-values
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write_verilog: dump zero width constants correctly
2019-07-18 15:31:27 +02:00
Clifford Wolf
56c00e871f
Remove old $pmux_safe code from write_verilog
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-17 11:49:04 +02:00
whitequark
4ff44d85a5
write_verilog: dump zero width constants correctly.
...
Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.
After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)
Fixes #948 (again).
2019-07-16 21:00:09 +00:00
N. Engelhardt
ab4b9e8db4
smt: handle failure of setrlimit syscall
2019-07-15 23:33:18 +08:00
Clifford Wolf
9112850800
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
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write_verilog: write RTLIL::Sa aka - as Verilog ?
2019-07-11 07:25:52 +02:00
Eddie Hung
375fcbe511
abc_flop to also get topologically sorted
2019-07-10 20:26:09 -07:00
Eddie Hung
ea6ffea2cd
Fix clk_pol for FD*_1
2019-07-10 20:10:20 -07:00
Eddie Hung
e603d719d6
Fix spacing
2019-07-10 19:04:22 -07:00
Eddie Hung
4a995c5d80
Change how to specify flops to ABC again
2019-07-10 17:54:56 -07:00
Eddie Hung
a092c48f03
Use split_tokens()
2019-07-10 17:34:51 -07:00
Eddie Hung
052060f109
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 16:05:41 -07:00
Clifford Wolf
6dd33be7ce
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
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write_verilog: fix placement of case attributes
2019-07-09 22:51:25 +02:00
whitequark
37bb6b5e96
write_verilog: fix placement of case attributes. NFC.
2019-07-09 19:14:03 +00:00
whitequark
6a29e1f5b7
write_verilog: write RTLIL::Sa aka - as Verilog ?.
...
Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.
2019-07-09 18:35:49 +00:00
Eddie Hung
00d8a9dce2
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore
...
Rename __builtin_bswap32 -> bswap32
2019-07-09 10:22:57 -07:00
Eddie Hung
5a0f2e43c7
Rename __builtin_bswap32 -> bswap32
2019-07-09 09:35:09 -07:00
whitequark
628437b01c
verilog_backend: dump attributes on SwitchRule.
...
This appears to be an omission.
2019-07-08 15:11:29 +00:00
whitequark
55c1f40277
verilog_backend: dump attributes on CaseRule, as comments.
...
Attributes are not permitted in that position by Verilog grammar.
2019-07-08 12:48:50 +00:00
whitequark
93bc5affd3
Allow attributes on individual switch cases in RTLIL.
...
The parser changes are slightly awkward. Consider the following IL:
process $0
<point 1>
switch \foo
<point 2>
case 1'1
assign \bar \baz
<point 3>
...
case
end
end
Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.
To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.
Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
Eddie Hung
10524064e9
write_xaiger to treat unknown cell connections as keep-s
2019-07-02 19:14:30 -07:00
Eddie Hung
69f4c039ce
Safe side: all flops have different mergeability class
2019-07-02 12:21:03 -07:00
Eddie Hung
a31e17182d
Refactor and cope with new abc_flop format
2019-07-01 11:50:34 -07:00
Eddie Hung
699d8e3939
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-01 10:44:42 -07:00
Eddie Hung
38d8806bd7
Add generic __builtin_bswap32 function
2019-06-28 09:59:47 -07:00
Eddie Hung
524af21317
Also fix write_aiger for UB
2019-06-28 09:55:07 -07:00
Eddie Hung
36e2eb06bb
Fix more potential for undefined behaviour due to container invalidation
2019-06-28 09:51:43 -07:00
Eddie Hung
9398921af1
Refactor for one "abc_carry" attribute on module
2019-06-27 16:07:14 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Eddie Hung
080a5ca536
Improve debugging message for comb loops
2019-06-26 20:02:38 -07:00
Eddie Hung
cec2292b0b
Merge remote-tracking branch 'origin/master' into xaig
2019-06-24 20:01:43 -07:00
Eddie Hung
7903ebe3e0
Carry in/out box ordering now move to end, not swap with end
2019-06-22 14:18:42 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
fddb027cab
Replace assert with error message
2019-06-21 17:18:04 -07:00
Eddie Hung
7074ec9cd5
Add log_push()/log_pop() inside write_xaiger
2019-06-21 17:17:29 -07:00
Eddie Hung
65c1199acd
One more workaround for gcc-4.8
2019-06-21 14:36:24 -07:00
Eddie Hung
bd7ec673dd
No point logging constant bit
2019-06-21 14:31:09 -07:00
Eddie Hung
70c93ea0c4
Move comment
2019-06-21 14:31:09 -07:00
Miodrag Milanovic
fde90f7f8e
Fix json formatting
2019-06-21 20:01:40 +02:00
Miodrag Milanovic
50e7221077
Add upto and offset to JSON ports
2019-06-21 19:47:25 +02:00
Clifford Wolf
f15def325c
Added JSON upto and offset
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 15:22:17 +02:00
Eddie Hung
6a336ca23e
Fix spacing
2019-06-20 22:30:20 -07:00
Eddie Hung
e21f01d938
Refactor bit2aig for less lookups
2019-06-20 22:10:43 -07:00
Eddie Hung
4422b7311b
Fix gcc invalidation behaviour for write_aiger
2019-06-20 22:10:43 -07:00
Eddie Hung
32f8014e12
Fix gcc error, due to dict invalidation during recursion
2019-06-20 22:10:43 -07:00
Eddie Hung
c4ea6fff65
Fix gcc invalidation behaviour for write_aiger
2019-06-20 21:56:47 -07:00
Eddie Hung
8e56cfb6bb
write_xaiger to flatten 1'bx/1'bz to 1'b0 again
2019-06-20 19:41:27 -07:00
Eddie Hung
ad36eb24c0
Fix different abc9 test
2019-06-20 19:41:27 -07:00
Eddie Hung
9faeba7a66
Fix broken abc9.v test due to inout being 1'bx
2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
4e5836a5fb
Handle COs driven by 1'bx
2019-06-20 17:38:04 -07:00
Eddie Hung
f2d541962e
write_xaiger to skip POs driven by 1'bx
2019-06-20 17:37:54 -07:00
Ben Widawsky
4a18e19fb8
Support filename rewrite in backends
...
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-18 14:39:52 -07:00
Clifford Wolf
c23bbc4291
Add timescale and generated-by header to yosys-smtbmc MkVcd
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-16 23:12:03 +02:00
Eddie Hung
0c59bc0b75
Cleanup
2019-06-16 10:42:00 -07:00
Eddie Hung
fb90d8c18c
Cleanup
2019-06-16 09:34:26 -07:00
Eddie Hung
6852c83bbe
Cleanup write_xaiger
2019-06-15 22:50:15 -07:00
Eddie Hung
bd2690e9b9
Preserve init of flops, and write into XAIG
2019-06-15 22:41:13 -07:00
Eddie Hung
2309459605
Do not treat $__ABC_FF_ as a user cell
2019-06-15 19:36:55 -07:00
Eddie Hung
0debea25a7
Update comment
2019-06-15 18:24:04 -07:00
Eddie Hung
c2f3f116d0
Use $__ABC_FF_ instead of $_FF_
2019-06-15 18:16:14 -07:00
Eddie Hung
6d74b3e004
Update comment
2019-06-15 09:36:02 -07:00
Eddie Hung
357d36ef4f
write_xaiger to treat abc_flop boxes as boxff for ABC
2019-06-15 09:07:03 -07:00
Eddie Hung
7ff8330d1e
Leave breadcrumb behind
2019-06-14 13:34:40 -07:00
Eddie Hung
46e69ee934
Remove redundant condition
2019-06-14 13:31:18 -07:00
Eddie Hung
9b55e69755
Revert "Cleanup/optimise toposort in write_xaiger"
...
This reverts commit 1948e7c846
.
Restores old toposort with optimisations
2019-06-14 13:29:36 -07:00
Eddie Hung
746f70a9ce
Update comment
2019-06-14 13:10:46 -07:00
Eddie Hung
0fa6a441f1
Check that whiteboxes are synthesisable
2019-06-14 13:08:38 -07:00
Eddie Hung
2d85725604
Get rid of compiler warnings
2019-06-14 13:07:56 -07:00