mirror of https://github.com/YosysHQ/yosys.git
Use abc_mergeability attr for "r" extension
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313d2478e9
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@ -85,7 +85,7 @@ struct XAigerWriter
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
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vector<SigBit> ff_bits;
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vector<std::pair<SigBit,int>> ff_bits;
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dict<SigBit, float> arrival_times;
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vector<pair<int, int>> aig_gates;
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@ -319,11 +319,12 @@ struct XAigerWriter
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auto abc_flop_q = r.first->second.q_port;
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SigBit q = cell->getPort(abc_flop_q);
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SigBit O = sigmap(q);
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if (O != q)
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alias_map[O] = q;
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undriven_bits.erase(O);
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ff_bits.emplace_back(q);
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log_assert(q == sigmap(q));
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undriven_bits.erase(q);
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auto it = cell->attributes.find(ID(abc_mergeability));
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log_assert(it != cell->attributes.end());
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ff_bits.emplace_back(q, it->second.as_int());
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cell->attributes.erase(it);
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auto arrival = r.first->second.q_arrival;
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if (arrival)
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@ -343,56 +344,57 @@ struct XAigerWriter
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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continue;
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}
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else {
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bool cell_known = inst_module || cell->known();
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for (const auto &c : cell->connections()) {
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if (c.second.is_fully_const()) continue;
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auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
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auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
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auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
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if (!is_input && !is_output)
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log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
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if (is_input) {
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for (auto b : c.second) {
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Wire *w = b.wire;
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if (!w) continue;
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if (!w->port_output || !cell_known) {
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SigBit I = sigmap(b);
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if (I != b)
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alias_map[b] = I;
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output_bits.insert(b);
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unused_bits.erase(b);
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bool cell_known = inst_module || cell->known();
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for (const auto &c : cell->connections()) {
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if (c.second.is_fully_const()) continue;
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auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
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auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
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auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
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if (!is_input && !is_output)
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log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
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if (!cell_known)
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keep_bits.insert(b);
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}
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if (is_input) {
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for (auto b : c.second) {
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Wire *w = b.wire;
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if (!w) continue;
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if (!w->port_output || !cell_known) {
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SigBit I = sigmap(b);
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if (I != b)
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alias_map[b] = I;
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output_bits.insert(b);
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unused_bits.erase(b);
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if (!cell_known)
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keep_bits.insert(b);
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}
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}
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if (is_output) {
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int arrival = 0;
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if (port_wire) {
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auto it = port_wire->attributes.find("\\abc_arrival");
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if (it != port_wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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arrival = it->second.as_int();
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}
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}
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if (is_output) {
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int arrival = 0;
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if (port_wire) {
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auto it = port_wire->attributes.find("\\abc_arrival");
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if (it != port_wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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arrival = it->second.as_int();
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}
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}
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for (auto b : c.second) {
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Wire *w = b.wire;
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if (!w) continue;
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input_bits.insert(b);
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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undriven_bits.erase(O);
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for (auto b : c.second) {
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Wire *w = b.wire;
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if (!w) continue;
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input_bits.insert(b);
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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undriven_bits.erase(O);
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if (arrival)
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arrival_times[b] = arrival;
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}
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if (arrival)
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arrival_times[b] = arrival;
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}
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}
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}
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@ -540,12 +542,15 @@ struct XAigerWriter
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undriven_bits.erase(bit);
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if (!undriven_bits.empty() && !holes_mode) {
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bool whole_module = module->design->selected_whole_module(module->name);
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undriven_bits.sort();
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for (auto bit : undriven_bits) {
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log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
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if (whole_module)
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log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
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input_bits.insert(bit);
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}
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log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
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if (whole_module)
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log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
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}
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init_map.sort();
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@ -576,7 +581,8 @@ struct XAigerWriter
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aig_map[bit] = 2*aig_m;
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}
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for (auto bit : ff_bits) {
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for (const auto &i : ff_bits) {
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const SigBit &bit = i.first;
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aig_m++, aig_i++;
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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@ -663,7 +669,8 @@ struct XAigerWriter
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aig_outputs.push_back(bit2aig(bit));
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}
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for (auto bit : ff_bits) {
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for (auto &i : ff_bits) {
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const SigBit &bit = i.first;
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aig_o++;
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aig_outputs.push_back(ff_aig_map.at(bit));
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}
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@ -853,9 +860,9 @@ struct XAigerWriter
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auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
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log_debug("flopNum = %d\n", GetSize(ff_bits));
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write_r_buffer(ff_bits.size());
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int mergeability_class = 1;
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for (auto bit : ff_bits) {
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write_r_buffer(mergeability_class++);
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for (const auto &i : ff_bits) {
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write_r_buffer(i.second);
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const SigBit &bit = i.first;
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write_i_buffer(arrival_times.at(bit, 0));
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//write_o_buffer(0);
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}
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@ -869,7 +876,8 @@ struct XAigerWriter
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std::stringstream s_buffer;
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auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
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write_s_buffer(ff_bits.size());
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for (auto bit : ff_bits) {
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for (const auto &i : ff_bits) {
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const SigBit &bit = i.first;
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auto it = bit.wire->attributes.find("\\init");
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if (it != bit.wire->attributes.end()) {
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auto init = it->second[bit.offset];
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