mirror of https://github.com/YosysHQ/yosys.git
Call "proc" if processes inside whiteboxes
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@ -706,7 +706,7 @@ struct XAigerWriter
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IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
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RTLIL::Module* box_module = module->design->module(derived_name);
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if (box_module->has_processes())
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log_error("ABC9 box '%s' contains processes!\n", box_module->name.c_str());
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Pass::call_on_module(module->design, box_module, "proc");
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int box_inputs = 0, box_outputs = 0;
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auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
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