mirror of https://github.com/YosysHQ/yosys.git
Do not sigmap keep bits inside write_xaiger
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@ -168,7 +168,7 @@ struct XAigerWriter
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}
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if (keep)
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keep_bits.insert(bit);
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keep_bits.insert(wirebit);
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if (wire->port_input || keep) {
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if (bit != wirebit)
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