mirror of https://github.com/YosysHQ/yosys.git
Preserve init of flops, and write into XAIG
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2309459605
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@ -258,8 +258,8 @@ struct XAigerWriter
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undriven_bits.erase(O);
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}
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}
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if (!abc_box_seen)
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abc_box_seen = inst_module->attributes.count("\\abc_box_id");
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log_assert(inst_module->attributes.count("\\abc_box_id"));
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abc_box_seen = true;
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ff_bits.emplace_back(d, q);
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}
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@ -696,7 +696,7 @@ struct XAigerWriter
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log_debug("ciNum = %zu\n", input_bits.size() + ff_bits.size() + ci_bits.size());
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write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
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log_debug("coNum = %zu\n", output_bits.size() + ff_bits.size() + co_bits.size());
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write_h_buffer(output_bits.size() + ff_bits.size()+ co_bits.size());
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write_h_buffer(output_bits.size() + ff_bits.size() + co_bits.size());
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log_debug("piNum = %zu\n", input_bits.size() + ff_bits.size());
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write_h_buffer(input_bits.size()+ ff_bits.size());
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log_debug("poNum = %zu\n", output_bits.size() + ff_bits.size());
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@ -780,7 +780,7 @@ struct XAigerWriter
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write_r_buffer(ff_bits.size());
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int mergeability_class = 1;
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for (auto cell : ff_bits)
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write_r_buffer(mergeability_class++);
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write_r_buffer(mergeability_class);
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f << "r";
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buffer_str = r_buffer.str();
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@ -788,6 +788,27 @@ struct XAigerWriter
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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std::stringstream s_buffer;
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auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
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write_s_buffer(ff_bits.size());
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for (auto &f : ff_bits) {
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RTLIL::SigBit q = f.second;
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auto it = q.wire->attributes.find("\\init");
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if (it != q.wire->attributes.end()) {
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auto init = it->second[q.offset];
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if (init == RTLIL::S1) {
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write_s_buffer(1);
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continue;
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}
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}
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write_s_buffer(0);
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}
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f << "s";
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buffer_str = s_buffer.str();
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buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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if (holes_module) {
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// NB: fixup_ports() will sort ports by name
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//holes_module->fixup_ports();
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@ -857,7 +878,11 @@ struct XAigerWriter
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if (output_bits.count(b)) {
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int o = ordered_outputs.at(b);
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output_lines[o] += stringf("output %lu %d %s\n", o - co_bits.size(), i, log_id(wire));
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int init = 2;
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auto it = init_map.find(b);
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if (it != init_map.end())
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init = it->second ? 1 : 0;
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output_lines[o] += stringf("output %lu %d %s %d\n", o - co_bits.size(), i, log_id(wire), init);
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continue;
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}
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