mirror of https://github.com/YosysHQ/yosys.git
Allow attributes on individual switch cases in RTLIL.
The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places.
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@ -204,6 +204,11 @@ void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const
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for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it)
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{
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for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) {
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f << stringf("%s attribute %s ", indent.c_str(), ait->first.c_str());
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dump_const(f, ait->second);
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f << stringf("\n");
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}
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f << stringf("%s case ", indent.c_str());
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for (size_t i = 0; i < (*it)->compare.size(); i++) {
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if (i > 0)
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@ -282,14 +282,14 @@ proc_stmt:
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} case_body sync_list TOK_END EOL;
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switch_stmt:
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attr_list TOK_SWITCH sigspec EOL {
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TOK_SWITCH sigspec EOL {
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RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
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rule->signal = *$3;
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rule->signal = *$2;
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rule->attributes = attrbuf;
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switch_stack.back()->push_back(rule);
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attrbuf.clear();
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delete $3;
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} switch_body TOK_END EOL;
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delete $2;
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} attr_list switch_body TOK_END EOL;
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attr_list:
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/* empty */ |
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@ -298,9 +298,11 @@ attr_list:
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switch_body:
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switch_body TOK_CASE {
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RTLIL::CaseRule *rule = new RTLIL::CaseRule;
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rule->attributes = attrbuf;
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switch_stack.back()->back()->cases.push_back(rule);
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switch_stack.push_back(&rule->switches);
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case_stack.push_back(rule);
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attrbuf.clear();
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} compare_list EOL case_body {
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switch_stack.pop_back();
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case_stack.pop_back();
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@ -319,12 +321,15 @@ compare_list:
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/* empty */;
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case_body:
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case_body attr_stmt |
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case_body switch_stmt |
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case_body assign_stmt |
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/* empty */;
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assign_stmt:
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TOK_ASSIGN sigspec sigspec EOL {
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if (attrbuf.size() != 0)
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rtlil_frontend_ilang_yyerror("dangling attribute");
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case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3));
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delete $2;
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delete $3;
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@ -1327,7 +1327,7 @@ public:
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#endif
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};
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struct RTLIL::CaseRule
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struct RTLIL::CaseRule : public RTLIL::AttrObject
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{
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std::vector<RTLIL::SigSpec> compare;
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std::vector<RTLIL::SigSig> actions;
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