write_verilog: dump $mem cell attributes.

The Verilog backend already dumps attributes on RTLIL::Memory objects but not on `$mem` cells.
2020-02-06 16:22:22 +00:00 · 2020-02-06 16:22:22 +00:00 · e95a8ba763
parent d44848328b
commit e95a8ba763
1 changed files with 1 additions and 0 deletions
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@ -1066,6 +1066,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		//  initial begin
 		//    memid[0] = ...
 		//  end
+		dump_attributes(f, indent.c_str(), cell->attributes);
 		f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset);
 		if (use_init)
 		{