mirror of https://github.com/YosysHQ/yosys.git
Get rid of output_port lookup
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3879ca1398
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d9fba95177
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@ -768,15 +768,14 @@ struct XAigerWriter
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box_outputs += GetSize(w);
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for (int i = 0; i < GetSize(w); i++) {
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if (GetSize(w) == 1)
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holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
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holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
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else
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holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
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holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
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holes_wire->port_output = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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if (holes_cell) {
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if (holes_cell)
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port_sig.append(holes_wire);
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}
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else
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holes_module->connect(holes_wire, State::S0);
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}
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@ -862,15 +861,6 @@ struct XAigerWriter
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// instead of per write_xaiger call
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Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
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dict<SigBit, Wire*> output_port;
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SigMap holes_sigmap(holes_module);
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for (auto port_name : holes_module->ports) {
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Wire *port = holes_module->wire(port_name);
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if (port->port_input)
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continue;
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output_port.insert(std::make_pair(holes_sigmap(port), port));
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}
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dict<SigSig, SigSig> replace;
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for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
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auto cell = it->second;
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@ -879,7 +869,11 @@ struct XAigerWriter
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SigBit Q = cell->getPort("\\Q");
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// Remove the DFF cell from what needs to be a combinatorial box
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it = holes_module->cells_.erase(it);
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Wire *port = output_port.at(Q);
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Wire *port;
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if (GetSize(Q.wire) == 1)
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port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
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else
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port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
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log_assert(port);
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// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
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// in order to extract the combinatorial control logic that feeds the box
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