mirror of https://github.com/YosysHQ/yosys.git
write_verilog: add -extmem option, to write split memory init files.
Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used.
This commit is contained in:
whitequark
parent
e907ee4fde
commit
3c643c57df
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@ -33,11 +33,11 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal, siminit;
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int auto_name_counter, auto_name_offset, auto_name_digits;
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bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit;
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int auto_name_counter, auto_name_offset, auto_name_digits, extmem_counter;
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std::map<RTLIL::IdString, int> auto_name_map;
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std::set<RTLIL::IdString> reg_wires, reg_ct;
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std::string auto_prefix;
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std::string auto_prefix, extmem_prefix;
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RTLIL::Module *active_module;
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dict<RTLIL::SigBit, RTLIL::State> active_initdata;
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@ -1069,14 +1069,64 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset);
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if (use_init)
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{
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f << stringf("%s" "initial begin\n", indent.c_str());
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for (int i=0; i<size; i++)
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if (extmem)
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{
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f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i);
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dump_const(f, cell->parameters["\\INIT"].extract(i*width, width));
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f << stringf(";\n");
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std::string extmem_filename = stringf("%s-%d.mem", extmem_prefix.c_str(), extmem_counter++);
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std::string extmem_filename_esc;
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for (auto c : extmem_filename)
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{
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if (c == '\n')
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extmem_filename_esc += "\\n";
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else if (c == '\t')
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extmem_filename_esc += "\\t";
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else if (c < 32)
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extmem_filename_esc += stringf("\\%03o", c);
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else if (c == '"')
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extmem_filename_esc += "\\\"";
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else if (c == '\\')
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extmem_filename_esc += "\\\\";
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else
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extmem_filename_esc += c;
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}
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f << stringf("%s" "initial $readmemb(\"%s\", %s);\n", indent.c_str(), extmem_filename_esc.c_str(), mem_id.c_str());
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std::ofstream extmem_f(extmem_filename, std::ofstream::trunc);
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if (extmem_f.fail())
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log_error("Can't open file `%s' for writing: %s\n", extmem_filename.c_str(), strerror(errno));
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else
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{
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for (int i=0; i<size; i++)
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{
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RTLIL::Const element = cell->parameters["\\INIT"].extract(i*width, width);
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for (int j=0; j<element.size(); j++)
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{
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switch (element[element.size()-j-1])
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{
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case State::S0: extmem_f << '0'; break;
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case State::S1: extmem_f << '1'; break;
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case State::Sx: extmem_f << 'x'; break;
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case State::Sz: extmem_f << 'z'; break;
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case State::Sa: extmem_f << '_'; break;
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case State::Sm: log_error("Found marker state in final netlist.");
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}
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}
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extmem_f << '\n';
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}
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}
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}
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else
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{
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f << stringf("%s" "initial begin\n", indent.c_str());
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for (int i=0; i<size; i++)
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{
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f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i);
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dump_const(f, cell->parameters["\\INIT"].extract(i*width, width));
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f << stringf(";\n");
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}
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f << stringf("%s" "end\n", indent.c_str());
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}
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f << stringf("%s" "end\n", indent.c_str());
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}
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// create a map : "edge clk" -> expressions within that clock domain
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@ -1777,8 +1827,16 @@ struct VerilogBackend : public Backend {
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log(" deactivates this feature and instead will write string constants\n");
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log(" as binary numbers.\n");
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log("\n");
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log(" -extmem\n");
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log(" instead of initializing memories using assignments to individual\n");
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log(" elements, use the '$readmemh' function to read initialization data\n");
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log(" from a file. This data is written to a file named by appending\n");
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log(" a sequential index to the Verilog filename and replacing the extension\n");
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log(" with '.mem', e.g. 'write_verilog -extmem foo.v' writes 'foo-1.mem',\n");
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log(" 'foo-2.mem' and so on.\n");
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log("\n");
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log(" -defparam\n");
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log(" Use 'defparam' statements instead of the Verilog-2001 syntax for\n");
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log(" use 'defparam' statements instead of the Verilog-2001 syntax for\n");
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log(" cell parameters.\n");
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log("\n");
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log(" -blackboxes\n");
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@ -1812,6 +1870,7 @@ struct VerilogBackend : public Backend {
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nodec = false;
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nohex = false;
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nostr = false;
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extmem = false;
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defparam = false;
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decimal = false;
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siminit = false;
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@ -1885,6 +1944,11 @@ struct VerilogBackend : public Backend {
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nostr = true;
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continue;
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}
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if (arg == "-extmem") {
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extmem = true;
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extmem_counter = 1;
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continue;
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}
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if (arg == "-defparam") {
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defparam = true;
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continue;
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@ -1912,6 +1976,12 @@ struct VerilogBackend : public Backend {
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break;
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}
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extra_args(f, filename, args, argidx);
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if (extmem)
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{
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if (filename.empty())
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log_cmd_error("Option -extmem must be used with a filename.\n");
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extmem_prefix = filename.substr(0, filename.rfind('.'));
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}
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design->sort();
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