mirror of https://github.com/YosysHQ/yosys.git
parent
6464dc35ec
commit
419ca5c207
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@ -174,7 +174,6 @@ struct XAigerWriter
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if (bit != wirebit)
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alias_map[bit] = wirebit;
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input_bits.insert(wirebit);
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undriven_bits.erase(bit);
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}
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if (wire->port_output || keep) {
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@ -182,8 +181,6 @@ struct XAigerWriter
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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if (!wire->port_input)
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unused_bits.erase(bit);
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}
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else
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log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
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@ -191,6 +188,12 @@ struct XAigerWriter
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}
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}
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for (auto bit : input_bits)
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undriven_bits.erase(sigmap(bit));
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for (auto bit : output_bits)
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if (!bit.wire->port_input)
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unused_bits.erase(bit);
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// TODO: Speed up toposort -- ultimately we care about
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// box ordering, but not individual AIG cells
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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