riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fold loop

This commit is contained in:
Eddie Hung 2019-11-25 15:43:37 -08:00
parent 68717dd03b
commit a30d5e1cc3
1 changed files with 3 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
backends/aiger/xaiger.cc
View File

@ -174,6 +174,7 @@ struct XAigerWriter
if (bit != wirebit)
alias_map[bit] = wirebit;
input_bits.insert(wirebit);
undriven_bits.erase(bit);
}
if (wire->port_output || keep) {
@ -181,6 +182,8 @@ struct XAigerWriter
if (bit != wirebit)
alias_map[wirebit] = bit;
output_bits.insert(wirebit);
if (!wire->port_input)
unused_bits.erase(bit);
}
else
log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
@ -188,12 +191,6 @@ struct XAigerWriter
}
}
for (auto bit : input_bits)
undriven_bits.erase(sigmap(bit));
for (auto bit : output_bits)
if (!bit.wire->port_input)
unused_bits.erase(bit);
// TODO: Speed up toposort -- ultimately we care about
// box ordering, but not individual AIG cells
dict<SigBit, pool<IdString>> bit_drivers, bit_users;