mirror of https://github.com/YosysHQ/yosys.git
Refactor to directly call ILANG_BACKEND::dump_const() + directly lookup src attribute
This commit is contained in:
Sahand Kashani
parent
f48fb26c0f
commit
018116e478
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@ -23,6 +23,7 @@
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#include "kernel/celltypes.h"
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#include "kernel/cellaigs.h"
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#include "kernel/log.h"
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#include "backends/ilang/ilang_backend.h"
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#include <algorithm>
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#include <string>
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#include <vector>
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@ -42,72 +43,18 @@ static const FDirection FD_OUT = 0x2;
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static const FDirection FD_INOUT = 0x3;
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static const int FIRRTL_MAX_DSH_WIDTH_ERROR = 20; // For historic reasons, this is actually one greater than the maximum allowed shift width
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// Shamelessly copied from ilang_backend.cc. Something better is surely possible here.
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void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true)
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std::string getFileinfo(const RTLIL::AttrObject *design_entity)
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{
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if (width < 0)
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width = data.bits.size() - offset;
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if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
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if (width == 32 && autoint) {
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int32_t val = 0;
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for (int i = 0; i < width; i++) {
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log_assert(offset+i < (int)data.bits.size());
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switch (data.bits[offset+i]) {
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case RTLIL::S0: break;
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case RTLIL::S1: val |= 1 << i; break;
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default: val = -1; break;
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}
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}
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if (val >= 0) {
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f << stringf("%d", val);
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return;
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}
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}
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f << stringf("%d'", width);
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for (int i = offset+width-1; i >= offset; i--) {
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log_assert(i < (int)data.bits.size());
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switch (data.bits[i]) {
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case RTLIL::S0: f << stringf("0"); break;
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case RTLIL::S1: f << stringf("1"); break;
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case RTLIL::Sx: f << stringf("x"); break;
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case RTLIL::Sz: f << stringf("z"); break;
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case RTLIL::Sa: f << stringf("-"); break;
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case RTLIL::Sm: f << stringf("m"); break;
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}
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}
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} else {
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f << stringf("\"");
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std::string str = data.decode_string();
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for (size_t i = 0; i < str.size(); i++) {
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if (str[i] == '\n')
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f << stringf("\\n");
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else if (str[i] == '\t')
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f << stringf("\\t");
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else if (str[i] < 32)
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f << stringf("\\%03o", str[i]);
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else if (str[i] == '"')
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f << stringf("\\\"");
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else if (str[i] == '\\')
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f << stringf("\\\\");
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else
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f << str[i];
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}
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f << stringf("\"");
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}
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}
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std::string src(design_entity->get_src_attribute());
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std::string getFileinfo(const dict<RTLIL::IdString, RTLIL::Const> &attributes)
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{
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std::ostringstream fileinfo;
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for (auto &it : attributes) {
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if (it.first == "\\src") {
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fileinfo << "@[";
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dump_const(fileinfo, it.second);
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fileinfo << "]";
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}
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if (!src.empty()) {
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fileinfo << "@[" << src << "]";
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}
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std::string fileinfo_str = fileinfo.str();
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// Remove quotes from src attribute as firrtl automatically escapes and
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// double-quotes them.
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std::string fileinfo_str(fileinfo.str());
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fileinfo_str.erase(std::remove(fileinfo_str.begin(), fileinfo_str.end(), '\"'), fileinfo_str.end());
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return fileinfo_str;
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@ -401,7 +348,7 @@ struct FirrtlWorker
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log_warning("No instance for %s.%s\n", cell_type.c_str(), cell_name.c_str());
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return;
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}
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auto cellFileinfo = getFileinfo(cell->attributes);
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auto cellFileinfo = getFileinfo(cell);
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wire_exprs.push_back(stringf("%s" "inst %s%s of %s %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), instanceOf.c_str(), cellFileinfo.c_str()));
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for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
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@ -467,14 +414,14 @@ struct FirrtlWorker
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void run()
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{
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auto moduleFileinfo = getFileinfo(module->attributes);
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auto moduleFileinfo = getFileinfo(module);
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f << stringf(" module %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
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vector<string> port_decls, wire_decls, cell_exprs, wire_exprs;
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for (auto wire : module->wires())
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{
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const auto wireName = make_id(wire->name);
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auto wireFileinfo = getFileinfo(wire->attributes);
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auto wireFileinfo = getFileinfo(wire);
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// If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
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if (wire->attributes.count("\\init")) {
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@ -517,7 +464,7 @@ struct FirrtlWorker
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string primop;
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bool always_uint = false;
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string y_id = make_id(cell->name);
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std::string cellFileinfo = getFileinfo(cell->attributes);
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std::string cellFileinfo = getFileinfo(cell);
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if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
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{
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@ -573,7 +520,7 @@ struct FirrtlWorker
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{
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string a_expr = make_expr(cell->getPort("\\A"));
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string b_expr = make_expr(cell->getPort("\\B"));
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std::string cellFileinfo = getFileinfo(cell->attributes);
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std::string cellFileinfo = getFileinfo(cell);
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wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
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if (a_signed) {
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@ -1037,7 +984,7 @@ struct FirrtlWorker
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for (auto wire : module->wires())
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{
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string expr;
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std::string wireFileinfo = getFileinfo(wire->attributes);
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std::string wireFileinfo = getFileinfo(wire);
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if (wire->port_input)
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continue;
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@ -1208,7 +1155,7 @@ struct FirrtlBackend : public Backend {
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if (top == nullptr)
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top = last;
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auto circuitFileinfo = getFileinfo(top->attributes);
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auto circuitFileinfo = getFileinfo(top);
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*f << stringf("circuit %s: %s\n", make_id(top->name), circuitFileinfo.c_str());
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for (auto module : design->modules())
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