riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Do not sigmap keep bits inside write_xaiger

This commit is contained in:
Eddie Hung 2019-11-25 15:42:07 -08:00
parent 6831510f5b
commit 7f0914a408
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
backends/aiger/xaiger.cc
View File

@ -183,7 +183,7 @@ struct XAigerWriter
}
if (keep)
keep_bits.insert(bit);
keep_bits.insert(wirebit);
if (wire->port_input || keep) {
if (bit != wirebit)