mirror of https://github.com/YosysHQ/yosys.git
Cleanup write_xaiger
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3ed95dae8d
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6852c83bbe
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@ -68,7 +68,7 @@ struct XAigerWriter
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
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vector<std::pair<SigBit,SigBit>> ff_bits;
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vector<SigBit> ff_bits;
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vector<pair<int, int>> aig_gates;
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vector<int> aig_latchin, aig_latchinit, aig_outputs;
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@ -237,31 +237,29 @@ struct XAigerWriter
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if (inst_flop) {
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toposort.node(cell->name);
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SigBit d, q;
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for (const auto &c : cell->connections()) {
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auto is_input = cell->input(c.first);
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auto is_output = cell->output(c.first);
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log_assert(is_input || is_output);
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RTLIL::Wire* port = inst_module->wire(c.first);
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if (is_input && port->attributes.count("\\abc_flop_d")) {
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d = c.second;
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SigBit d = c.second;
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SigBit I = sigmap(d);
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if (I != d)
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alias_map[I] = d;
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unused_bits.erase(d);
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}
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if (is_output && port->attributes.count("\\abc_flop_q")) {
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q = c.second;
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SigBit q = c.second;
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SigBit O = sigmap(q);
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if (O != q)
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alias_map[O] = q;
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undriven_bits.erase(O);
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ff_bits.emplace_back(q);
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}
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}
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log_assert(inst_module->attributes.count("\\abc_box_id"));
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abc_box_seen = true;
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ff_bits.emplace_back(d, q);
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}
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else if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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abc_box_seen = true;
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@ -515,8 +513,7 @@ struct XAigerWriter
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aig_map[bit] = 2*aig_m;
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}
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for (auto &f : ff_bits) {
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RTLIL::SigBit bit = f.second;
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for (auto bit : ff_bits) {
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aig_m++, aig_i++;
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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@ -598,9 +595,8 @@ struct XAigerWriter
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aig_outputs.push_back(bit2aig(bit));
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}
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for (auto &f : ff_bits) {
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for (auto bit : ff_bits) {
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aig_o++;
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RTLIL::SigBit bit = f.second;
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aig_outputs.push_back(ff_aig_map.at(bit));
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}
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}
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@ -791,11 +787,10 @@ struct XAigerWriter
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std::stringstream s_buffer;
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auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
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write_s_buffer(ff_bits.size());
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for (auto &f : ff_bits) {
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RTLIL::SigBit q = f.second;
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auto it = q.wire->attributes.find("\\init");
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if (it != q.wire->attributes.end()) {
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auto init = it->second[q.offset];
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for (auto bit : ff_bits) {
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auto it = bit.wire->attributes.find("\\init");
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if (it != bit.wire->attributes.end()) {
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auto init = it->second[bit.offset];
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if (init == RTLIL::S1) {
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write_s_buffer(1);
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continue;
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