mirror of https://github.com/YosysHQ/yosys.git
Revert "Only xaig if GetSize(output_bits) > 0"
This reverts commit 7b646101e9.
This commit is contained in:
Eddie Hung
parent
7b646101e9
commit
4d123b7638
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@ -575,178 +575,176 @@ struct XAigerWriter
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f << "c";
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if (GetSize(output_bits) > 0) {
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auto write_buffer = [](std::stringstream &buffer, int i32) {
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int32_t i32_be = to_big_endian(i32);
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buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
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};
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std::stringstream h_buffer;
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auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
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write_h_buffer(1);
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log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ci_bits));
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write_h_buffer(input_bits.size() + ci_bits.size());
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log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(co_bits));
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write_h_buffer(output_bits.size() + GetSize(co_bits));
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log_debug("piNum = %d\n", GetSize(input_bits));
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write_h_buffer(input_bits.size());
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log_debug("poNum = %d\n", GetSize(output_bits));
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write_h_buffer(output_bits.size());
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log_debug("boxNum = %d\n", GetSize(box_list));
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write_h_buffer(box_list.size());
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auto write_buffer = [](std::stringstream &buffer, int i32) {
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int32_t i32_be = to_big_endian(i32);
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buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
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};
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std::stringstream h_buffer;
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auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
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write_h_buffer(1);
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log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ci_bits));
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write_h_buffer(input_bits.size() + ci_bits.size());
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log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(co_bits));
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write_h_buffer(output_bits.size() + GetSize(co_bits));
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log_debug("piNum = %d\n", GetSize(input_bits));
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write_h_buffer(input_bits.size());
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log_debug("poNum = %d\n", GetSize(output_bits));
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write_h_buffer(output_bits.size());
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log_debug("boxNum = %d\n", GetSize(box_list));
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write_h_buffer(box_list.size());
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auto write_buffer_float = [](std::stringstream &buffer, float f32) {
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buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
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};
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std::stringstream i_buffer;
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auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
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for (auto bit : input_bits)
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write_i_buffer(arrival_times.at(bit, 0));
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//std::stringstream o_buffer;
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//auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
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//for (auto bit : output_bits)
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// write_o_buffer(0);
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auto write_buffer_float = [](std::stringstream &buffer, float f32) {
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buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
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};
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std::stringstream i_buffer;
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auto write_i_buffer = std::bind(write_buffer_float, std::ref(i_buffer), std::placeholders::_1);
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for (auto bit : input_bits)
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write_i_buffer(arrival_times.at(bit, 0));
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//std::stringstream o_buffer;
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//auto write_o_buffer = std::bind(write_buffer_float, std::ref(o_buffer), std::placeholders::_1);
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//for (auto bit : output_bits)
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// write_o_buffer(0);
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if (!box_list.empty()) {
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RTLIL::Module *holes_module = module->design->addModule("$__holes__");
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log_assert(holes_module);
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if (!box_list.empty()) {
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RTLIL::Module *holes_module = module->design->addModule("$__holes__");
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log_assert(holes_module);
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int port_id = 1;
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int box_count = 0;
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for (auto cell : box_list) {
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RTLIL::Module* box_module = module->design->module(cell->type);
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int box_inputs = 0, box_outputs = 0;
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Cell *holes_cell = nullptr;
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if (box_module->get_bool_attribute("\\whitebox")) {
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holes_cell = holes_module->addCell(cell->name, cell->type);
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holes_cell->parameters = cell->parameters;
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}
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int port_id = 1;
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int box_count = 0;
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for (auto cell : box_list) {
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RTLIL::Module* box_module = module->design->module(cell->type);
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int box_inputs = 0, box_outputs = 0;
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Cell *holes_cell = nullptr;
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if (box_module->get_bool_attribute("\\whitebox")) {
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holes_cell = holes_module->addCell(cell->name, cell->type);
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holes_cell->parameters = cell->parameters;
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}
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// NB: Assume box_module->ports are sorted alphabetically
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// (as RTLIL::Module::fixup_ports() would do)
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for (const auto &port_name : box_module->ports) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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RTLIL::Wire *holes_wire;
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RTLIL::SigSpec port_wire;
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if (w->port_input) {
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for (int i = 0; i < GetSize(w); i++) {
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box_inputs++;
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holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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if (holes_cell)
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port_wire.append(holes_wire);
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}
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if (!port_wire.empty())
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holes_cell->setPort(w->name, port_wire);
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}
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if (w->port_output) {
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box_outputs += GetSize(w);
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for (int i = 0; i < GetSize(w); i++) {
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if (GetSize(w) == 1)
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holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
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else
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holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
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holes_wire->port_output = true;
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// NB: Assume box_module->ports are sorted alphabetically
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// (as RTLIL::Module::fixup_ports() would do)
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for (const auto &port_name : box_module->ports) {
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RTLIL::Wire *w = box_module->wire(port_name);
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log_assert(w);
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RTLIL::Wire *holes_wire;
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RTLIL::SigSpec port_wire;
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if (w->port_input) {
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for (int i = 0; i < GetSize(w); i++) {
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box_inputs++;
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holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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if (holes_cell)
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port_wire.append(holes_wire);
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else
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holes_module->connect(holes_wire, State::S0);
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}
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if (!port_wire.empty())
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holes_cell->setPort(w->name, port_wire);
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if (holes_cell)
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port_wire.append(holes_wire);
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}
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if (!port_wire.empty())
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holes_cell->setPort(w->name, port_wire);
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}
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if (w->port_output) {
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box_outputs += GetSize(w);
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for (int i = 0; i < GetSize(w); i++) {
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if (GetSize(w) == 1)
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holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
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else
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holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
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holes_wire->port_output = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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if (holes_cell)
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port_wire.append(holes_wire);
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else
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holes_module->connect(holes_wire, State::S0);
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}
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if (!port_wire.empty())
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holes_cell->setPort(w->name, port_wire);
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}
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write_h_buffer(box_inputs);
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write_h_buffer(box_outputs);
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write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
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write_h_buffer(box_count++);
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}
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std::stringstream r_buffer;
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auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
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write_r_buffer(0);
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f << "r";
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std::string buffer_str = r_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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if (holes_module) {
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log_push();
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// NB: fixup_ports() will sort ports by name
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//holes_module->fixup_ports();
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holes_module->check();
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holes_module->design->selection_stack.emplace_back(false);
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RTLIL::Selection& sel = holes_module->design->selection_stack.back();
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sel.select(holes_module);
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// TODO: Should not need to opt_merge if we only instantiate
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// each box type once...
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Pass::call(holes_module->design, "opt_merge -share_all");
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Pass::call(holes_module->design, "flatten -wb");
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// TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
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// instead of per write_xaiger call
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Pass::call(holes_module->design, "techmap");
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Pass::call(holes_module->design, "aigmap");
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for (auto cell : holes_module->cells())
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if (!cell->type.in("$_NOT_", "$_AND_"))
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log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
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holes_module->design->selection_stack.pop_back();
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// Move into a new (temporary) design so that "clean" will only
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// operate (and run checks on) this one module
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RTLIL::Design *holes_design = new RTLIL::Design;
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holes_module->design->modules_.erase(holes_module->name);
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holes_design->add(holes_module);
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Pass::call(holes_design, "clean -purge");
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module, true /* holes_mode */);
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writer.write_aiger(a_buffer, false /*ascii_mode*/);
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delete holes_design;
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f << "a";
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std::string buffer_str = a_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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log_pop();
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}
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write_h_buffer(box_inputs);
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write_h_buffer(box_outputs);
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write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
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write_h_buffer(box_count++);
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}
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f << "h";
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std::string buffer_str = h_buffer.str();
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std::stringstream r_buffer;
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auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
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write_r_buffer(0);
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f << "r";
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std::string buffer_str = r_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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f << "i";
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buffer_str = i_buffer.str();
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buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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//f << "o";
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//buffer_str = o_buffer.str();
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//buffer_size_be = to_big_endian(buffer_str.size());
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//f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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//f.write(buffer_str.data(), buffer_str.size());
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if (holes_module) {
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log_push();
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// NB: fixup_ports() will sort ports by name
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//holes_module->fixup_ports();
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holes_module->check();
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holes_module->design->selection_stack.emplace_back(false);
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RTLIL::Selection& sel = holes_module->design->selection_stack.back();
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sel.select(holes_module);
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// TODO: Should not need to opt_merge if we only instantiate
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// each box type once...
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Pass::call(holes_module->design, "opt_merge -share_all");
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Pass::call(holes_module->design, "flatten -wb");
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// TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
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// instead of per write_xaiger call
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Pass::call(holes_module->design, "techmap");
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Pass::call(holes_module->design, "aigmap");
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for (auto cell : holes_module->cells())
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if (!cell->type.in("$_NOT_", "$_AND_"))
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log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
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holes_module->design->selection_stack.pop_back();
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// Move into a new (temporary) design so that "clean" will only
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// operate (and run checks on) this one module
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RTLIL::Design *holes_design = new RTLIL::Design;
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holes_module->design->modules_.erase(holes_module->name);
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holes_design->add(holes_module);
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Pass::call(holes_design, "clean -purge");
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std::stringstream a_buffer;
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XAigerWriter writer(holes_module, true /* holes_mode */);
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writer.write_aiger(a_buffer, false /*ascii_mode*/);
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delete holes_design;
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f << "a";
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std::string buffer_str = a_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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log_pop();
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}
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}
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f << "h";
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std::string buffer_str = h_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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f << "i";
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buffer_str = i_buffer.str();
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buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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//f << "o";
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//buffer_str = o_buffer.str();
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//buffer_size_be = to_big_endian(buffer_str.size());
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//f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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//f.write(buffer_str.data(), buffer_str.size());
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f << stringf("Generated by %s\n", yosys_version_str);
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}
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