mirror of https://github.com/YosysHQ/yosys.git
write_xaiger: cope with abc9_arrival as string of ints
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47a1fd3f4a
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3177437224
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@ -185,6 +185,7 @@ struct XAigerWriter
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}
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}
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std::vector<int> arrivals;
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for (auto cell : module->cells()) {
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if (cell->type == "$_NOT_")
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{
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@ -224,13 +225,15 @@ struct XAigerWriter
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}
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (inst_module) {
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if (inst_module && inst_module->get_blackbox_attribute()) {
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auto it = cell->attributes.find("\\abc9_box_seq");
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if (it != cell->attributes.end()) {
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int abc9_box_seq = it->second.as_int();
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if (GetSize(box_list) <= abc9_box_seq)
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box_list.resize(abc9_box_seq+1);
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box_list[abc9_box_seq] = cell;
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// Only flop boxes may have arrival times
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// (all others are combinatorial)
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if (!inst_module->get_bool_attribute("\\abc9_flop"))
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continue;
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}
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@ -238,16 +241,26 @@ struct XAigerWriter
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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if (port_wire->port_output) {
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int arrival = 0;
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arrivals.clear();
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auto it = port_wire->attributes.find("\\abc9_arrival");
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if (it != port_wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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arrival = it->second.as_int();
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if (it->second.flags == 0)
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arrivals.emplace_back(it->second.as_int());
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else
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for (const auto &tok : split_tokens(it->second.decode_string()))
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arrivals.push_back(atoi(tok.c_str()));
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}
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if (!arrivals.empty()) {
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if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
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log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
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GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
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auto jt = arrivals.begin();
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for (auto bit : sigmap(conn.second)) {
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arrival_times[bit] = *jt;
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if (arrivals.size() > 1)
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jt++;
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}
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}
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if (arrival)
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for (auto bit : sigmap(conn.second))
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arrival_times[bit] = arrival;
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}
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}
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}
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