mirror of https://github.com/YosysHQ/yosys.git
Do not sigmap!
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parent
0ca397f087
commit
1b5d2de1d4
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@ -355,7 +355,7 @@ struct XAigerWriter
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log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
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if (is_input) {
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for (auto b : sigmap(c.second)) {
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for (auto b : c.second) {
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Wire *w = b.wire;
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if (!w) continue;
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if (!w->port_output || !cell_known) {
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@ -381,7 +381,7 @@ struct XAigerWriter
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}
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}
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for (auto b : sigmap(c.second)) {
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for (auto b : c.second) {
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Wire *w = b.wire;
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if (!w) continue;
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input_bits.insert(b);
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