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Deprecate `abc_scc_break` attribute

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Eddie Hung 2019-08-20 15:10:01 -07:00
parent e273ed5275
commit 0ca397f087
1 changed files with 0 additions and 8 deletions
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@ -409,14 +409,6 @@ Verilog Attributes and non-standard features
blackbox or whitebox definition to a corresponding entry in a `abc9`
box-file.
- The port attribute ``abc_scc_break`` indicates a module input port that will
be treated as a primary output during `abc9` techmapping. Doing so eliminates
the possibility of a strongly-connected component (i.e. a combinatorial loop)
existing. Typically, this is specified for sequential inputs on otherwise
combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D`
port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths
as a combinatorial loop.
- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
carry-out (if output port) ports of a box. This information is necessary for
`abc9` to preserve the integrity of carry-chains. Specifying this attribute