mirror of https://github.com/YosysHQ/yosys.git
Cleanup/optimise toposort in write_xaiger
This commit is contained in:
Eddie Hung
parent
a5425a2f7e
commit
1948e7c846
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@ -167,51 +167,12 @@ struct XAigerWriter
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if (!bit.wire->port_input)
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unused_bits.erase(bit);
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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SigMap topomap;
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topomap.database = sigmap.database;
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bool abc_box_seen = false;
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for (auto cell : module->cells()) {
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RTLIL::Module* inst_module = module->design->module(cell->type);
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bool builtin_type = yosys_celltypes.cell_known(cell->type);
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bool abc_type = inst_module && inst_module->attributes.count("\\abc_box_id");
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if (!holes_mode) {
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toposort.node(cell->name);
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for (const auto &conn : cell->connections()) {
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if (!builtin_type && !abc_type)
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continue;
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if (!cell->type.in("$_NOT_", "$_AND_")) {
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if (builtin_type) {
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if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
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continue;
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if (cell->type == "$memrd" && conn.first == "\\DATA")
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continue;
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}
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if (inst_module) {
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RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
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log_assert(inst_module_port);
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if (inst_module_port->port_output && inst_module_port->attributes.count("\\abc_flop_q"))
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continue;
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}
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}
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if (cell->input(conn.first)) {
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// Ignore inout for the sake of topographical ordering
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if (cell->output(conn.first)) continue;
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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}
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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}
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if (cell->type == "$_NOT_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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@ -219,6 +180,8 @@ struct XAigerWriter
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unused_bits.erase(A);
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undriven_bits.erase(Y);
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not_map[Y] = A;
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if (!holes_mode)
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topomap.add(Y, A);
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continue;
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}
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@ -241,6 +204,10 @@ struct XAigerWriter
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unused_bits.erase(B);
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undriven_bits.erase(Y);
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and_map[Y] = make_pair(A, B);
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if (!holes_mode) {
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topomap.add(Y, A);
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topomap.add(Y, B);
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}
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continue;
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}
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@ -252,6 +219,7 @@ struct XAigerWriter
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// continue;
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//}
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RTLIL::Module* inst_module = module->design->module(cell->type);
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bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
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if (inst_flop) {
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SigBit d, q;
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@ -322,20 +290,46 @@ struct XAigerWriter
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//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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if (abc_box_seen) {
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if (abc_box_seen && !holes_mode) {
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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for (auto cell : module->cells()) {
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (!inst_module || !inst_module->attributes.count("\\abc_box_id"))
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continue;
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toposort.node(cell->name);
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for (const auto &conn : cell->connections()) {
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if (cell->input(conn.first)) {
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// Ignore inout for the sake of topographical ordering
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if (cell->output(conn.first)) continue;
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for (auto bit : topomap(conn.second))
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if (bit.wire)
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bit_users[bit].insert(cell->name);
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}
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if (cell->output(conn.first)) {
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RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
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log_assert(inst_module_port);
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if (inst_module_port->attributes.count("\\abc_flop_q"))
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continue;
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for (auto bit : topomap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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}
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}
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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pool<RTLIL::Module*> abc_carry_modules;
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#if 0
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#if 1
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toposort.analyze_loops = true;
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#endif
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bool no_loops = toposort.sort();
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#if 0
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#if 1
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unsigned i = 0;
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for (auto &it : toposort.loops) {
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log(" loop %d", i++);
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@ -346,13 +340,14 @@ struct XAigerWriter
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#endif
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log_assert(no_loops);
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pool<RTLIL::Module*> abc_carry_modules;
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for (auto cell_name : toposort.sorted) {
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RTLIL::Cell *cell = module->cell(cell_name);
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RTLIL::Module* box_module = module->design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc_box_id"))
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continue;
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log_assert(box_module);
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log_assert(box_module->attributes.count("\\abc_box_id"));
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if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
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if (!abc_carry_modules.count(box_module) && box_module->attributes.count("\\abc_carry")) {
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RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
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RTLIL::Wire* last_in = nullptr, *last_out = nullptr;
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for (const auto &port_name : box_module->ports) {
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@ -448,8 +443,6 @@ struct XAigerWriter
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}
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box_list.emplace_back(cell);
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}
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// TODO: Free memory from toposort, bit_drivers, bit_users
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}
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for (auto bit : input_bits) {
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