mirror of https://github.com/YosysHQ/yosys.git
Revert "Cleanup/optimise toposort in write_xaiger"
This reverts commit 1948e7c846.
Restores old toposort with optimisations
This commit is contained in:
Eddie Hung
parent
746f70a9ce
commit
9b55e69755
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@ -185,9 +185,8 @@ struct XAigerWriter
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if (!bit.wire->port_input)
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unused_bits.erase(bit);
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SigMap topomap;
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topomap.database = sigmap.database;
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc_box_seen = false;
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for (auto cell : module->selected_cells()) {
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@ -198,8 +197,11 @@ struct XAigerWriter
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unused_bits.erase(A);
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undriven_bits.erase(Y);
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not_map[Y] = A;
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if (!holes_mode)
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topomap.add(Y, A);
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if (!holes_mode) {
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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}
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continue;
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}
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@ -223,12 +225,16 @@ struct XAigerWriter
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undriven_bits.erase(Y);
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and_map[Y] = make_pair(A, B);
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if (!holes_mode) {
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topomap.add(Y, A);
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topomap.add(Y, B);
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_users[B].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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}
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continue;
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}
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log_assert(!holes_mode);
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//if (cell->type == "$initstate")
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//{
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// SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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@ -265,11 +271,26 @@ struct XAigerWriter
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// }
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// if (!abc_box_seen)
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// abc_box_seen = inst_module->attributes.count("\\abc_box_id");
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// ff_bits.emplace_back(d, q);
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//}
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/*else*/ if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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abc_box_seen = true;
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if (!holes_mode) {
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toposort.node(cell->name);
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for (const auto &conn : cell->connections()) {
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if (cell->input(conn.first)) {
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// Ignore inout for the sake of topographical ordering
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if (cell->output(conn.first)) continue;
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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}
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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}
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}
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else {
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for (const auto &c : cell->connections()) {
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@ -309,45 +330,19 @@ struct XAigerWriter
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}
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if (abc_box_seen && !holes_mode) {
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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for (auto cell : module->selected_cells()) {
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (!inst_module || !inst_module->attributes.count("\\abc_box_id"))
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continue;
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toposort.node(cell->name);
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for (const auto &conn : cell->connections()) {
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if (cell->input(conn.first)) {
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// Ignore inout for the sake of topographical ordering
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if (cell->output(conn.first)) continue;
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for (auto bit : topomap(conn.second))
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if (bit.wire)
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bit_users[bit].insert(cell->name);
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}
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if (cell->output(conn.first)) {
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RTLIL::Wire* inst_module_port = inst_module->wire(conn.first);
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log_assert(inst_module_port);
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//if (inst_module_port->attributes.count("\\abc_flop_q"))
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// continue;
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for (auto bit : topomap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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}
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}
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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#if 1
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pool<RTLIL::Module*> abc_carry_modules;
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#if 0
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toposort.analyze_loops = true;
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#endif
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bool no_loops = toposort.sort();
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#if 1
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#if 0
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unsigned i = 0;
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for (auto &it : toposort.loops) {
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log(" loop %d", i++);
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@ -358,14 +353,13 @@ struct XAigerWriter
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#endif
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log_assert(no_loops);
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pool<RTLIL::Module*> abc_carry_modules;
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for (auto cell_name : toposort.sorted) {
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RTLIL::Cell *cell = module->cell(cell_name);
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RTLIL::Module* box_module = module->design->module(cell->type);
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log_assert(box_module);
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log_assert(box_module->attributes.count("\\abc_box_id"));
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if (!box_module || !box_module->attributes.count("\\abc_box_id"))
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continue;
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if (!abc_carry_modules.count(box_module) && box_module->attributes.count("\\abc_carry")) {
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if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
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RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
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RTLIL::Wire* last_in = nullptr, *last_out = nullptr;
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for (const auto &port_name : box_module->ports) {
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@ -461,6 +455,8 @@ struct XAigerWriter
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}
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box_list.emplace_back(cell);
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}
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// TODO: Free memory from toposort, bit_drivers, bit_users
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}
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for (auto bit : input_bits) {
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