mirror of https://github.com/YosysHQ/yosys.git
write_xaiger: get rid of external_bits dict
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@ -78,7 +78,7 @@ struct XAigerWriter
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Module *module;
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SigMap sigmap;
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pool<SigBit> input_bits, output_bits, external_bits;
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<SigBit> ci_bits, co_bits;
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