mirror of https://github.com/YosysHQ/yosys.git
write_xaiger to treat abc_flop boxes as boxff for ABC
This commit is contained in:
Eddie Hung
parent
bf312043d4
commit
357d36ef4f
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@ -66,7 +66,6 @@ struct XAigerWriter
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, ff_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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//pool<SigBit> initstate_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
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vector<std::pair<SigBit,SigBit>> ff_bits;
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@ -97,10 +96,6 @@ struct XAigerWriter
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{
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aig_map[bit] = -1;
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//if (initstate_bits.count(bit)) {
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// log_assert(initstate_ff > 0);
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// aig_map[bit] = initstate_ff;
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//} else
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if (not_map.count(bit)) {
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int a = bit2aig(not_map.at(bit)) ^ 1;
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aig_map[bit] = a;
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@ -207,16 +202,6 @@ struct XAigerWriter
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continue;
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}
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//if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
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//{
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// SigBit D = sigmap(cell->getPort("\\D").as_bit());
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// SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
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// unused_bits.erase(D);
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// undriven_bits.erase(Q);
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// ff_map[Q] = D;
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// continue;
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//}
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if (cell->type == "$_AND_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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@ -237,61 +222,62 @@ struct XAigerWriter
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log_assert(!holes_mode);
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//if (cell->type == "$initstate")
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// FIXME: Should short here, rather than provide $_DFF_[NP]_
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// to ABC as a user cell
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//if (cell->type.in(/*"$_FF_",*/ "$_DFF_N_", "$_DFF_P_"))
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//{
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// SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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// undriven_bits.erase(Y);
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// initstate_bits.insert(Y);
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// SigBit D = sigmap(cell->getPort("\\D").as_bit());
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// SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
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// alias_map[Q] = D;
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// continue;
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//}
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RTLIL::Module* inst_module = module->design->module(cell->type);
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//bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
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//if (inst_flop) {
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// SigBit d, q;
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// for (const auto &c : cell->connections()) {
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// auto is_input = cell->input(c.first);
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// auto is_output = cell->output(c.first);
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// log_assert(is_input || is_output);
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// RTLIL::Wire* port = inst_module->wire(c.first);
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// for (auto b : c.second.bits()) {
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// if (is_input && port->attributes.count("\\abc_flop_d")) {
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// d = b;
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// SigBit I = sigmap(d);
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// if (I != d)
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// alias_map[I] = d;
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// unused_bits.erase(d);
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// }
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// if (is_output && port->attributes.count("\\abc_flop_q")) {
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// q = b;
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// SigBit O = sigmap(q);
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// if (O != q)
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// alias_map[O] = q;
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// undriven_bits.erase(O);
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// }
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// }
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// }
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// if (!abc_box_seen)
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// abc_box_seen = inst_module->attributes.count("\\abc_box_id");
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// ff_bits.emplace_back(d, q);
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//}
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/*else*/ if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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RTLIL::Module* inst_module = !holes_mode ? module->design->module(cell->type) : nullptr;
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bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false;
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if (inst_flop) {
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toposort.node(cell->name);
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SigBit d, q;
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for (const auto &c : cell->connections()) {
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auto is_input = cell->input(c.first);
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auto is_output = cell->output(c.first);
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log_assert(is_input || is_output);
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RTLIL::Wire* port = inst_module->wire(c.first);
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if (is_input && port->attributes.count("\\abc_flop_d")) {
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d = c.second;
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SigBit I = sigmap(d);
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if (I != d)
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alias_map[I] = d;
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unused_bits.erase(d);
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}
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if (is_output && port->attributes.count("\\abc_flop_q")) {
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q = c.second;
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SigBit O = sigmap(q);
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if (O != q)
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alias_map[O] = q;
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undriven_bits.erase(O);
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}
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}
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if (!abc_box_seen)
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abc_box_seen = inst_module->attributes.count("\\abc_box_id");
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ff_bits.emplace_back(d, q);
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}
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else if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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abc_box_seen = true;
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if (!holes_mode) {
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toposort.node(cell->name);
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for (const auto &conn : cell->connections()) {
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if (cell->input(conn.first)) {
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// Ignore inout for the sake of topographical ordering
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if (cell->output(conn.first)) continue;
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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}
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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toposort.node(cell->name);
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for (const auto &conn : cell->connections()) {
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if (cell->input(conn.first)) {
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// Ignore inout for the sake of topographical ordering
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if (cell->output(conn.first)) continue;
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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}
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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}
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else {
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@ -555,17 +541,17 @@ struct XAigerWriter
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// }
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//}
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for (auto it : ff_map) {
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aig_m++, aig_l++;
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aig_map[it.first] = 2*aig_m;
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ordered_latches[it.first] = aig_l-1;
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if (init_map.count(it.first) == 0)
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aig_latchinit.push_back(2);
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else
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aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
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}
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//for (auto it : ff_map) {
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// aig_m++, aig_l++;
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// aig_map[it.first] = 2*aig_m;
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// ordered_latches[it.first] = aig_l-1;
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// if (init_map.count(it.first) == 0)
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// aig_latchinit.push_back(2);
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// else
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// aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
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//}
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//if (!initstate_bits.empty() || !init_inputs.empty()) {
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//if (!init_inputs.empty()) {
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// aig_m++, aig_l++;
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// initstate_ff = 2*aig_m+1;
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// aig_latchinit.push_back(0);
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@ -589,16 +575,16 @@ struct XAigerWriter
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// }
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//}
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for (auto it : ff_map) {
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int a = bit2aig(it.second);
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int l = ordered_latches[it.first];
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if (zinit_mode && aig_latchinit.at(l) == 1)
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aig_latchin.push_back(a ^ 1);
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else
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aig_latchin.push_back(a);
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}
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//for (auto it : ff_map) {
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// int a = bit2aig(it.second);
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// int l = ordered_latches[it.first];
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// if (zinit_mode && aig_latchinit.at(l) == 1)
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// aig_latchin.push_back(a ^ 1);
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// else
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// aig_latchin.push_back(a);
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//}
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//if (!initstate_bits.empty() || !init_inputs.empty())
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//if (!init_inputs.empty())
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// aig_latchin.push_back(1);
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for (auto &c : co_bits) {
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@ -617,7 +603,6 @@ struct XAigerWriter
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RTLIL::SigBit bit = f.second;
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aig_outputs.push_back(ff_aig_map.at(bit));
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}
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}
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void write_aiger(std::ostream &f, bool ascii_mode)
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@ -639,14 +624,14 @@ struct XAigerWriter
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for (int i = 0; i < aig_i; i++)
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f << stringf("%d\n", 2*i+2);
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for (int i = 0; i < aig_l; i++) {
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if (zinit_mode || aig_latchinit.at(i) == 0)
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f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 1)
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f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 2)
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f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
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}
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//for (int i = 0; i < aig_l; i++) {
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// if (zinit_mode || aig_latchinit.at(i) == 0)
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// f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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// else if (aig_latchinit.at(i) == 1)
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// f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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// else if (aig_latchinit.at(i) == 2)
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// f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
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//}
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for (int i = 0; i < aig_obc; i++)
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f << stringf("%d\n", aig_outputs.at(i));
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@ -665,14 +650,14 @@ struct XAigerWriter
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}
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else
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{
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for (int i = 0; i < aig_l; i++) {
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if (zinit_mode || aig_latchinit.at(i) == 0)
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f << stringf("%d\n", aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 1)
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f << stringf("%d 1\n", aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 2)
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f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
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}
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//for (int i = 0; i < aig_l; i++) {
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// if (zinit_mode || aig_latchinit.at(i) == 0)
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// f << stringf("%d\n", aig_latchin.at(i));
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// else if (aig_latchinit.at(i) == 1)
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// f << stringf("%d 1\n", aig_latchin.at(i));
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// else if (aig_latchinit.at(i) == 2)
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// f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
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//}
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for (int i = 0; i < aig_obc; i++)
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f << stringf("%d\n", aig_outputs.at(i));
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@ -789,21 +774,19 @@ struct XAigerWriter
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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/*if (!ff_bits.empty())*/ {
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std::stringstream r_buffer;
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auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
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log_debug("flopNum = %zu\n", ff_bits.size());
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write_r_buffer(ff_bits.size());
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//int mergeability_class = 1;
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//for (auto cell : ff_bits)
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// write_r_buffer(mergeability_class++);
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std::stringstream r_buffer;
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auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
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log_debug("flopNum = %zu\n", ff_bits.size());
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write_r_buffer(ff_bits.size());
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int mergeability_class = 1;
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for (auto cell : ff_bits)
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write_r_buffer(mergeability_class++);
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f << "r";
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std::string buffer_str = r_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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}
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f << "r";
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buffer_str = r_buffer.str();
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buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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if (holes_module) {
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// NB: fixup_ports() will sort ports by name
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@ -885,14 +868,14 @@ struct XAigerWriter
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// continue;
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//}
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if (ordered_latches.count(sig[i])) {
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int l = ordered_latches.at(sig[i]);
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if (zinit_mode && (aig_latchinit.at(l) == 1))
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latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
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else
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latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
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continue;
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}
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//if (ordered_latches.count(sig[i])) {
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// int l = ordered_latches.at(sig[i]);
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// if (zinit_mode && (aig_latchinit.at(l) == 1))
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// latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
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// else
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// latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
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// continue;
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//}
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if (verbose_map) {
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if (aig_map.count(sig[i]) == 0)
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