mirror of https://github.com/YosysHQ/yosys.git
Get rid of (* abc9_keep *) in write_xaiger too
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6dc63e84ef
commit
11577b46fc
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@ -250,7 +250,12 @@ struct XAigerWriter
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (inst_module) {
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bool abc9_box = inst_module->attributes.count("\\abc9_box_id") && !cell->get_bool_attribute("\\abc9_keep");
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bool abc9_box = inst_module->attributes.count("\\abc9_box_id");
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bool abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
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// The lack of an abc9_mergeability attribute indicates that
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// we do want to keep this flop, so do not treat it as a box
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if (abc9_flop && !cell->attributes.count("\\abc9_mergeability"))
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abc9_box = false;
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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@ -279,15 +284,15 @@ struct XAigerWriter
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}
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}
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if (abc9_box) {
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abc9_box_seen = true;
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if (abc9_box) {
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abc9_box_seen = true;
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toposort.node(cell->name);
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toposort.node(cell->name);
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if (inst_module->get_bool_attribute("\\abc9_flop"))
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flop_boxes.push_back(cell);
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continue;
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}
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if (abc9_flop)
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flop_boxes.push_back(cell);
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continue;
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}
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}
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bool cell_known = inst_module || cell->known();
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@ -322,11 +327,12 @@ struct XAigerWriter
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SigBit d;
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if (r.second) {
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for (const auto &conn : cell->connections()) {
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const SigSpec &rhs = conn.second;
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if (!rhs.is_bit())
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if (!conn.second.is_bit())
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continue;
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if (!ff_bits.count(rhs))
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d = conn.second;
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if (!ff_bits.count(d))
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continue;
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r.first->second.first = conn.first;
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Module *inst_module = module->design->module(cell->type);
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Wire *wire = inst_module->wire(conn.first);
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@ -337,7 +343,6 @@ struct XAigerWriter
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
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r.first->second.second = jt->second.as_int();
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}
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d = rhs;
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log_assert(d == sigmap(d));
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break;
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}
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@ -399,8 +404,7 @@ struct XAigerWriter
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log_assert(cell);
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RTLIL::Module* box_module = module->design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc9_box_id")
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|| cell->get_bool_attribute("\\abc9_keep"))
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if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
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continue;
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bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
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@ -434,7 +438,6 @@ struct XAigerWriter
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
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if (carry_in != IdString()) {
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log_assert(carry_out != IdString());
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r.first->second.push_back(carry_in);
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r.first->second.push_back(carry_out);
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}
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