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1466 Commits

Author SHA1 Message Date
tangxifan c0b1d76a5e [script] change default tool paths for OpenFPGA flow scripts 2022-08-18 11:02:21 -07:00
tangxifan 6ce1d4804c [test] deploy new test case to basic regression tests 2022-08-01 21:05:05 -07:00
tangxifan 9ea4a7c90f [script] fixed a bug 2022-08-01 19:18:41 -07:00
tangxifan 8b17bf1b1c [test] add a new test case to validate that .act file is not required when power analysis flow is off 2022-08-01 18:44:47 -07:00
tangxifan 55c7b75ab6 [script] even when power analysis mode is turned off, if users define a act file, still use it 2022-08-01 18:13:57 -07:00
root 0da44ad1fc [script] now .act file is no longer required in openfpga_flow/task when power analysis option is off 2022-08-02 08:02:28 +08:00
tangxifan 35fe858035 [test] fixed a few bugs 2022-07-28 12:06:16 -07:00
tangxifan ca9122ddb9 [test] fixed a bug 2022-07-28 11:57:47 -07:00
tangxifan ec31e124b7 [test] reworked test case on pcf2place 2022-07-28 11:51:56 -07:00
tangxifan 23f98d6a3b [engine] fixed a few bugs 2022-07-26 13:55:29 -07:00
tangxifan 353de4546f [test] add 'write_fabric_io_info' command to test cases 2022-07-26 13:48:54 -07:00
taoli4rs 347a29f27c Fix test name in basic regression test script. 2022-07-20 21:05:31 -07:00
taoli4rs 3762a3aae4 Code clean up based on review. 2022-07-20 14:34:44 -07:00
taoli4rs cfc0d08060 Add constrain_pin_location command in openfpga; add full flow test. 2022-07-20 11:51:00 -07:00
tangxifan 4b9431b132 [test] avoid XML bitstream output when can go beyond github runners' disk space 2022-05-25 18:45:26 +08:00
tangxifan 9832722056 [test] now add QuickLogic memory bank to fpga bitstream regression tests 2022-05-25 11:42:32 +08:00
tangxifan 86347a9d49 [test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols 2022-05-25 11:19:49 +08:00
tangxifan 7d694acf32 [test] debugging basic reg test paths 2022-05-23 11:21:36 +08:00
tangxifan b41cbad5d3 [test] force to run git diff under root directory 2022-05-23 10:32:43 +08:00
tangxifan 488a934097 [test] give abs path for git diff in basic regression tests 2022-05-23 09:12:33 +08:00
tangxifan 0dc7caf3b7 [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00
tangxifan 751d87b8e3 [test] fix a bug in detect changes in golden netlists 2022-05-22 13:06:47 +08:00
tangxifan 6719a9aa26 [test] update golden netlists/testbenches etc. 2022-05-22 13:03:01 +08:00
ganeshgore 17c4e9a1bb
Merge branch 'master' into binder 2022-05-10 19:58:17 -06:00
tangxifan d7e854eae7 [test] deploy new test to ci 2022-05-09 17:23:57 +08:00
tangxifan 7ed1548c6e [arch] fixed a few bugs 2022-05-09 17:22:48 +08:00
tangxifan 9f56e61342 [arch] syntax 2022-05-09 17:13:57 +08:00
tangxifan 0afe3a6d33 [HDL] update dff map rules to support negative triggered ffs 2022-05-09 16:58:18 +08:00
tangxifan 22c4d72358 [test] add a test case to validate negative edge-triggered ff 2022-05-09 16:57:42 +08:00
tangxifan 9c7868cfab [hdl] add a counter design which is triggered by negative edges 2022-05-09 16:41:21 +08:00
tangxifan 812af4f722 [arch] add arch that supports negative edge triggered flip-flop 2022-05-09 16:32:01 +08:00
tangxifan c8ff3fc8dc [test] add regression test to validate compilation of openfpga cell library files 2022-05-09 16:00:51 +08:00
tangxifan d4992fd9ad [HDL] Add a multi-mode ff which can support posedge and negedge 2022-05-09 15:52:17 +08:00
Ganesh Gore daae02a614 Minor documentation update 2022-05-08 13:03:16 -06:00
Ganesh Gore 522982c9ba Adde vtr_benchmarks_template for demo 2022-05-06 22:40:36 -06:00
Ganesh Gore 9473523b6b Added VTR arch without fracturable lut 2022-05-06 11:05:16 -06:00
Ganesh Gore 275cda081e [Bugfix] Typo 2022-05-05 08:40:21 -06:00
Ganesh Gore e845b62322 Update regession tasks 2022-05-05 01:46:19 -06:00
Ganesh Gore 1e243650b9 Added option to copy example projects 2022-05-03 14:06:16 -06:00
Ganesh Gore 21c3dbf611 Added regression for template project 2022-05-02 23:23:45 -06:00
Ganesh Gore 9891e42f7a Added template task 2022-05-02 11:49:16 -06:00
tangxifan 9bd66d531e [Test] Deploy the new test case to basic regression tests 2022-04-13 16:06:27 +08:00
tangxifan efc25aa66e [Script] Fixed a bug in wrong paths 2022-04-13 16:04:33 +08:00
tangxifan 5beefda3bd [Test] Add a new test case to validate the fix_pins option 2022-04-13 15:55:21 +08:00
tangxifan 576b9c2d8f [Script] Disable SDC writer in multiclock examples 2022-03-20 11:05:29 +08:00
tangxifan 3e3a65223c [Test] Deploy new test case to basic regression tests 2022-03-20 11:04:07 +08:00
tangxifan f8845f7d3a [Test] Add a test case to validate separated clock pins in global port 2022-03-20 11:02:07 +08:00
tangxifan c8da85cc24 [Doc] Update naming convention for OpenFPGA architecture files 2022-03-20 10:51:55 +08:00
tangxifan a1e2d9c864 [Arch] Add a new example openfpga arch where clock ports are independent 2022-03-20 10:50:31 +08:00
tangxifan 9f7a182433 [Arch] Typo 2022-02-24 09:51:26 -08:00
tangxifan fdaf97e60d [Test] Update test case by using GPIO with config_done signals 2022-02-24 09:49:34 -08:00
tangxifan fcaff28e24 [HDL] Add a new IO cell with config_done support 2022-02-24 09:46:55 -08:00
tangxifan a615c9d4e3 [Test] Rename test cases 2022-02-24 09:43:41 -08:00
tangxifan e443a4567d [Arch] Typo 2022-02-23 22:09:26 -08:00
tangxifan b27a04eb24 [Test] Now test case has a config done CCFF 2022-02-23 22:07:11 -08:00
tangxifan cf31879b20 [Test] Deploy new test to basic regression tests 2022-02-23 16:03:56 -08:00
tangxifan 245c7b1e45 [Test] Add a new test case to validate config enable signal in preconfigured testbenches 2022-02-23 16:02:00 -08:00
tangxifan e33ba667e4 [Test] Add missing file 2022-02-20 10:59:44 -08:00
tangxifan f30de1085c [Test] Cover all the related testcase about bus group 2022-02-19 23:33:16 -08:00
tangxifan b4202f52b4 [Test] debugging 2022-02-19 23:26:29 -08:00
tangxifan 785bb1633d [Test] trying to see if we support busgroup per benchmark in task configuration file 2022-02-19 23:23:36 -08:00
tangxifan 7645d5332d [Test] Update bug group examples on the big endian support 2022-02-18 23:09:03 -08:00
tangxifan 68644ea0f6 [Test] Add the new test to basic regression tests 2022-02-18 15:44:07 -08:00
tangxifan f0ce1e79a3 [Test] Added a new test to validate bus group in full testbench 2022-02-18 15:43:21 -08:00
tangxifan fe9e0ff977 [Test] Add the new test to basic regression tests 2022-02-18 15:38:53 -08:00
tangxifan c897a64ad5 [Script] Add a new example script to test full testbenches using bus group features 2022-02-18 15:37:42 -08:00
tangxifan 223575cf3e [Test] Added a new test for bus group on full testbenches 2022-02-18 15:33:29 -08:00
tangxifan 85c893c94c [Test] Add new test to basic regression tests 2022-02-18 15:30:08 -08:00
tangxifan 5ab84e1861 [Test] Add a new test for bus group 2022-02-18 15:29:33 -08:00
tangxifan b4d59fdd1e [Test] Update bus group file due to little and big endian conversion during yosys/vpr 2022-02-18 15:02:08 -08:00
tangxifan 36543f7f2f [Script] Support simplified rewriting for Yosys on output verilog 2022-02-18 14:54:39 -08:00
tangxifan 8ba3d06392 [Test] Fixed bugs in simulation settings 2022-02-18 12:36:22 -08:00
tangxifan a4d5172b7c [Test] Fixed bugs that causes VPR failed 2022-02-18 12:31:29 -08:00
tangxifan 43d852d8a1 [Test] Add the bus group test case to basic regression tests 2022-02-18 12:27:25 -08:00
tangxifan 7176037bc4 [Test] Added a new test about bus group 2022-02-18 12:26:00 -08:00
tangxifan 73e6ee964d [Script] Add a new example script showing how to use bus group features 2022-02-18 12:25:34 -08:00
tangxifan f02f3c10d4 [Test] Fix bugs on the remaining implicit verilog test cases 2022-02-15 16:49:15 -08:00
tangxifan 074811a612 [Script] Now counter benchmarks should pass on the implicit verilog test case 2022-02-15 16:47:14 -08:00
tangxifan 1370be0817 [Script] Fixing bugs 2022-02-15 16:44:51 -08:00
tangxifan 8be0868a3b [Test] Update test case which uses counter benchmarks: adding pin constraints 2022-02-15 16:29:06 -08:00
tangxifan 430580f138 [HDL] Fix a typo 2022-02-15 16:09:14 -08:00
tangxifan a7786efde1 [HDL] Now dual-clock counter has only 1 reset pin 2022-02-15 16:07:50 -08:00
tangxifan f002c79a61 [Test] Adapt pin constraints due to changes in pin names 2022-02-15 16:06:46 -08:00
tangxifan b533fd17d5 [Test] Rework pin constraints that cause problems 2022-02-15 15:41:16 -08:00
tangxifan 9ef7ad64d8 [Test] Simplify paths 2022-02-15 15:35:21 -08:00
tangxifan 7121513396 [HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work 2022-02-15 15:21:08 -08:00
tangxifan 74045fc7a1 [Script] Fix a bug 2022-02-14 23:11:42 -08:00
tangxifan 2990eb7406 [Script] Fixed a bug in task run when removing previous runs 2022-02-14 22:54:16 -08:00
tangxifan d0fe8d96fa [Test] Update template scripts and assoicated test cases by offering more options 2022-02-14 16:03:48 -08:00
tangxifan d667102a43 [Test] Add new test case to regression tests 2022-02-14 15:58:53 -08:00
tangxifan 70363effa4 [Test] Add a new test to validate 8-bit counters using full testbenches 2022-02-14 15:57:55 -08:00
tangxifan 2fb1df11bb [Script] Add a new example script 2022-02-14 15:54:07 -08:00
tangxifan 7ef808cbe4 [Test] Update pin constraints for different counter benchmarks 2022-02-14 15:28:03 -08:00
tangxifan 570c1b10dc [Test] Add dedicated pin constraints for counter designs 2022-02-14 13:54:48 -08:00
tangxifan 85011824e2 [Test] Enable Verilog-to-Verification flow for counter8 benchmarks 2022-02-14 13:15:55 -08:00
tangxifan 6630c17c23 [Test] Use preconfigured testbench template to run counter8 tests 2022-02-14 13:07:31 -08:00
tangxifan da3f9ccb80 [Test] Truncating counter designs in each task 2022-02-14 12:22:19 -08:00
tangxifan 0268814fc6 [Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests 2022-02-14 12:20:56 -08:00
tangxifan 1d3c9ff192 [Script] Adapt python scripts to support include directory 2022-02-01 13:55:25 -08:00
tangxifan 27ac2fafe5 [Test] Add the new test case to regression tests 2022-02-01 13:45:46 -08:00
tangxifan 532af96243 [Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench 2022-02-01 13:44:47 -08:00
tangxifan 35c7968c98 [Script] Add a new example openfpga shell script 2022-02-01 13:40:22 -08:00
tangxifan 09ef516de8 [Script] Tune OpenFPGA shell script to enable testing on relative paths 2022-01-31 14:23:13 -08:00
tangxifan 9871fe88fb [Test] Typo fix 2022-01-31 13:03:45 -08:00
tangxifan da8fc0f5d4 [Test] Add a new test case to validate ``--use_relative_path`` 2022-01-31 13:02:19 -08:00
tangxifan e59ea91ad6 [Script] Fixed a bug which causes errors 2022-01-26 11:49:32 -08:00
tangxifan f8ef3df560 [Test] Now use 4x4 fabric in testing write_rr_gsb commands 2022-01-26 11:41:48 -08:00
tangxifan a9042318cf [Test] Deploy the test case to regression tests 2022-01-26 11:26:17 -08:00
tangxifan 3b7588cd48 [Test] Rename test case to be consistent with the name of options 2022-01-26 11:25:54 -08:00
tangxifan 6b26ed0819 [Test] Add test cases on writing gsb files 2022-01-26 11:22:39 -08:00
tangxifan 5db049522d [Script] Add an example script about write GSB 2022-01-26 11:22:23 -08:00
tangxifan 11e045992d [Test] Now only compare on the golden netlist changes to branch 2022-01-25 21:24:10 -08:00
tangxifan 23795d6474 [Test] Update golden netlists 2022-01-25 20:37:08 -08:00
tangxifan a9e6b7c12e [FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled 2022-01-25 20:33:49 -08:00
tangxifan c2c827ee10 [Script] Fix a bug in git-diff for regression tests 2022-01-25 20:27:41 -08:00
tangxifan fedb1bd2e3 [Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp 2022-01-25 16:41:36 -08:00
tangxifan 5c0f63ddd9 [Test] Update regression tests for the new test about ``--no_time_stamp`` 2022-01-25 16:30:48 -08:00
tangxifan 6e778a74ee [Test] Add golden reference for files outputted without time stamp 2022-01-25 16:24:25 -08:00
tangxifan 2bee59c6ca [Test] Add the testcase to validate ``--no_time_stamp`` 2022-01-25 16:21:15 -08:00
tangxifan dd803dd1de [Test] Remove unused tests 2022-01-25 16:16:58 -08:00
tangxifan e4cfa2222f [Script] Add an example script to test option ``--no_time_stamp`` 2022-01-25 16:16:39 -08:00
tangxifan dd40057992 [Script] Fixed a bug which causes errors when removing run-directory 2022-01-25 13:56:42 -08:00
Aram Kostanyan 758453f725 Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections. 2022-01-21 02:21:00 +05:00
Aram Kostanyan 397f2e71f1 Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task. 2022-01-19 20:43:26 +05:00
Aram Kostanyan bd158311c5 Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark. 2022-01-18 14:07:41 +05:00
Aram Kostanyan 588ee14920 Merge branch 'master' into issue-483 2022-01-18 13:38:12 +05:00
Aram Kostanyan fb2e4377c8 Added missing changes from previous commit. 2022-01-17 19:42:40 +05:00
Aram Kostanyan 6a4cc340a3 Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
Awais Abbas 469b3a960c basic reg test updated 2022-01-14 15:44:26 +05:00
Awais Abbas 793e40cb95 basic_reg test for yosys-only flow added in OpenFPGA regression test scripts 2022-01-14 15:39:26 +05:00
Awais Abbas 598c5e6b75 Test case for yosys-only flow added 2022-01-14 15:37:47 +05:00
Awais Abbas fc52a4696c Yosys only support added in OpenFPGA 2022-01-06 14:44:11 +05:00
tangxifan 27caeb1d1f [Arch] Patched VPR arch 2022-01-02 20:47:22 -08:00
tangxifan 384a1e58d6 [Arch] Patch architecture using DSP with registers 2022-01-02 20:44:43 -08:00
tangxifan e3baec63f8 [Arch] Bug fix on architecture with registerable DSP 2022-01-02 20:35:48 -08:00
tangxifan f667065f75 [Arch] Bug fix in DSP with registers architecture 2022-01-02 20:34:26 -08:00
tangxifan 9c476ed5db [Arch] Syntax error fix 2022-01-02 20:27:00 -08:00
tangxifan 628191da5f [Test] Add new test case (DSP with registers) into FPGA-Verilog regression tests 2022-01-02 20:21:58 -08:00
tangxifan 824a03bdca [Flow] Patch new test case 2022-01-02 20:20:36 -08:00
tangxifan 48355d1fc3 [Benchmark] Add pipelined multiplier benchmark to test DSP block with registers 2022-01-02 20:16:59 -08:00
tangxifan 55da99f4ca [Flow] Add a new test case to validate DSP with registers 2022-01-02 20:08:23 -08:00
tangxifan 62b4a0b7ff [Flow] Add openfpga arch for DSP with registers 2022-01-02 19:59:33 -08:00
tangxifan 7598455497 [Doc] Update naming convention for architecture files 2022-01-02 19:51:09 -08:00
tangxifan 48491fcf52 [Flow] Add example architecture for DSP with input and output registers 2022-01-02 19:47:39 -08:00
tangxifan 81966c2131 [Doc] Update README for DSP blocks 2022-01-02 18:27:37 -08:00
nadeemyaseen-rs 236910cde4 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-12-09 00:00:21 +05:00
nadeemyaseen-rs 06fb4b0ece Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-11-25 00:00:22 +05:00
coolbreeze413 3c14373abf revert unnecessary task.conf changes 2021-11-19 19:07:09 +05:30
coolbreeze413 9ca8ab4fa2 minor change to task.conf to check CI 2021-11-19 18:49:37 +05:30
coolbreeze413 b86bd1ca68 re-enable counter_5clock,sdc_controller, lut_adder tests 2021-11-19 18:06:06 +05:30
coolbreeze413 31379062e3 remove minor comments 2021-11-18 18:40:15 +05:30
nadeemyaseen-rs 1ea56b2d18 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-11-18 00:00:55 +05:00
coolbreeze413 91094305bd enable all tests except 15 and 19 2021-11-17 20:56:12 +05:30
Lalit Sharma fe74c42252 Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure 2021-11-12 01:46:06 -08:00
coolbreeze413 840fa399c6 enable single counter test (fails, needs debug) 2021-11-09 21:36:33 +05:30
coolbreeze413 3fa373f8bc add plugins, set yosys install for plugin 2021-11-04 07:22:09 +05:30
Aram Kostanyan a707226ba6 Added 'basic_tests/verific_test' test case into regression tests suite. 2021-11-01 18:33:33 +05:00
Aram Kostanyan b332a5a1b4 Added 'basic_tests/verific_test' test-case. 2021-11-01 18:20:57 +05:00
tangxifan ff264c00a2 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-31 11:51:34 -07:00
tangxifan 0d882f57b1
Merge branch 'master' into yosys+verific_support 2021-10-30 22:49:21 -07:00
tangxifan 0d14aa4cb8 [Flow] Add comments to clarify the limitations 2021-10-30 19:17:11 -07:00
tangxifan 7f999d03c6 [Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade 2021-10-30 18:05:39 -07:00
tangxifan 370e3fef83 [Test] Now use pre-configured testbench when verifying signal gen microbenchmarks 2021-10-30 18:03:59 -07:00
tangxifan 7455990ead [Flow] bug fix 2021-10-30 16:52:32 -07:00
tangxifan c8e9dfbeda [Test] bug fix 2021-10-30 16:50:57 -07:00
tangxifan 27b82d1473 [Flow] bug fix 2021-10-30 16:09:31 -07:00
tangxifan a4cfc84930 [Test] Bug fix 2021-10-30 16:00:47 -07:00
tangxifan 335347a74f [Test] Bug fix 2021-10-30 15:48:25 -07:00
tangxifan 6277234125 [Flow] bug fix in BRAM-oriented yosys scripts 2021-10-30 15:34:30 -07:00
tangxifan be47e78289 [Arch] Change arch for Sapone test 2021-10-30 15:23:19 -07:00
tangxifan e6cc3c4942 [Flow] Enable flatten for dff-related yosys scripts 2021-10-30 15:12:34 -07:00
tangxifan ad5cce0ae8 [Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals 2021-10-30 15:11:07 -07:00
tangxifan 8dea7e80e6 [Flow] Update yosys script to not use sdff and dffe 2021-10-30 14:56:54 -07:00
tangxifan 40d11a45d9 [Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade 2021-10-30 14:49:56 -07:00
tangxifan b7ad61227d [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF 2021-10-30 14:47:37 -07:00
tangxifan ec184ef532 [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF 2021-10-30 14:46:12 -07:00
tangxifan 0b770f3330 [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 14:36:43 -07:00
tangxifan 59a622a910 [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 14:34:37 -07:00
tangxifan 978c60e75b [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 13:29:38 -07:00
tangxifan 18bab18032 [Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release 2021-10-30 13:20:58 -07:00
tangxifan 16de60e943 [Test] Turn off ACE2 run in bitstream generation only flows 2021-10-30 12:31:14 -07:00
tangxifan 94328351be [Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts 2021-10-30 12:00:06 -07:00
tangxifan 0a449cc24c [HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected 2021-10-30 11:45:01 -07:00
tangxifan 9c06041ce4 [Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff` 2021-10-30 11:27:40 -07:00
Aram Kostanyan a355977420 Adding Yosys+Verific support. 2021-10-29 18:34:27 +05:00
tangxifan b8d5920529 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-28 15:45:58 -07:00
Aram Kostanyan 2eef21a1af Fixed port names for mult_36x36 2021-10-26 19:14:43 +05:00
nadeemyaseen-rs 274252438a Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-10-20 20:13:46 +05:00
Christophe Alexandre c42acec81e Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py 2021-10-18 10:45:35 +00:00
Christophe Alexandre c3dd704bf3 Fixing typo in run_fpga_flow.py 2021-10-18 09:13:42 +00:00
Christophe Alexandre d411967159 Fixing small typo in run_fpga_flow.py 2021-10-15 10:01:12 +00:00
nadeemyaseen-rs e0cfd46ec7 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-10-14 19:25:31 +05:00
tangxifan b2c4e3314e [Test] Bug fix in test cases 2021-10-11 10:28:09 -07:00
tangxifan 8566e2a0cd [Test] Renaming test case to follow naming convention as other fabric key test cases 2021-10-11 09:56:23 -07:00
tangxifan 2bf203cd00 [Test] Deploy the new test to basic regression test 2021-10-11 09:54:39 -07:00
tangxifan b8b02d37d5 [Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file 2021-10-11 09:53:23 -07:00
tangxifan cdcb07256b [Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization 2021-10-11 09:49:22 -07:00
tangxifan 982a324e0d [Test] Temporarily disable some tests; Will go back later 2021-10-10 23:30:50 -07:00
tangxifan 40fd89fdb4 [arch] Update fabric key for multi-region 2021-10-10 22:03:49 -07:00
tangxifan 8f9e564cd5 [Test] Add the new test to basic regression test 2021-10-09 20:45:23 -07:00