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1167 Commits

Author SHA1 Message Date
tangxifan a67196178e [Test] Now use 'write_full_testbench' in configuration frame test cases 2021-06-07 13:58:15 -06:00
tangxifan 27fa15603a [Tool] Patch test case due to changes in the template script 2021-06-04 18:17:47 -06:00
tangxifan e9fa44cc25 [Tool] Add fast configuration to the write bitstream command in example shell script 2021-06-04 16:24:56 -06:00
tangxifan 5f96d440ec [Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration 2021-06-04 11:48:05 -06:00
tangxifan ec203d3a5c [Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases 2021-06-04 11:35:23 -06:00
tangxifan 2068291de0 [Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases 2021-06-04 11:32:49 -06:00
tangxifan aa4e1f5f9a [Test] Update test case which uses write_full_testbench openfpga shell script 2021-06-04 11:29:43 -06:00
tangxifan f5e90c9467 [Script] Update openfpga shell script with fast configuration option 2021-06-04 11:28:10 -06:00
tangxifan ebe30fc070 [Test] Deploy write full testbench to multi-head configuration chain test case 2021-06-03 17:08:33 -06:00
tangxifan 8fc90637e0 [Script] Update write_full_testbench example script to support custom device layout in VPR 2021-06-03 17:08:08 -06:00
tangxifan 1e9f6eb439 [Test] update configuration chain test to use new testbench 2021-06-03 15:53:27 -06:00
tangxifan 51ca62a464 [Script] Add example script for write_full_testbench command 2021-06-03 15:48:59 -06:00
Andrew Pond 12b44e0eca added configuration benchmark files 2021-05-13 10:04:23 -06:00
tangxifan c33ca464dc [Test] Deploy new tests to regression test 2021-05-07 12:06:46 -06:00
tangxifan 2baf3ddd2f [Test] Add test cases for 'report_bitstream_distribution' command 2021-05-07 12:06:24 -06:00
tangxifan 7dc7c1b4f5 [Script] Add example openfpga shell script showing how to use 'report_bitstream_distribution' command 2021-05-07 12:05:47 -06:00
tangxifan f1658cb735 [Test] Deploy blinking to test cases 2021-05-06 15:17:45 -06:00
tangxifan 16fff90607 [Benchmark] Add microbenchmark 1-bit blinking 2021-05-06 15:17:27 -06:00
tangxifan f77b81fe5b [Arch] recover the mem16k arch as it is used in other test cases 2021-04-28 15:05:30 -06:00
tangxifan bc34efe337 [Arch] Bug fix in the architecture using BRAM spanning two columns 2021-04-28 14:32:17 -06:00
tangxifan a5e40fbb21
Merge branch 'master' into micro_benchmarks 2021-04-28 14:27:58 -06:00
tangxifan 870432e7f1 [Test] Patch regression test script due to the change of DPRAM test case 2021-04-28 12:45:52 -06:00
tangxifan b72d4bd807 [Test] Update test case for 1kbit DPRAM architectures 2021-04-28 11:28:53 -06:00
tangxifan 117cea295d [Arch] Patch architecture to be compatible with pin names of DPRAM cell 2021-04-28 11:28:23 -06:00
tangxifan a571b063b6 [Benchmark] Add 1k DPRAM benchmark which can fit new arch 2021-04-28 11:26:31 -06:00
tangxifan c24edbd674 [Script] Update yosys script due to arch changes in DPRAM sizes 2021-04-28 10:55:59 -06:00
tangxifan ec4b60f3cc [Arch] Add example arch using 1-kbit DPRAM 2021-04-28 10:47:17 -06:00
tangxifan be98775ae5 [Arch] Reduce the size of DPRAM in example architecture to accelerate testing 2021-04-28 10:45:10 -06:00
tangxifan 5c729657ef [Test] Bug fix in test case for DPRAM whose width = 2 2021-04-28 10:31:22 -06:00
tangxifan 79b27a6329 [Arch] Patch arch using DPRAM block with wide = 2 2021-04-28 10:29:09 -06:00
tangxifan 63309ba72b [HDL] Patch dpram cell 2021-04-27 23:42:31 -06:00
tangxifan 411af10933 [Script] Patch yosys script for 16kbit dual port RAM 2021-04-27 23:41:47 -06:00
tangxifan 834657f2da [Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes 2021-04-27 23:41:14 -06:00
tangxifan 0bec4b3f32 [Test] Update task configuration to use proper openfpgashell script 2021-04-27 23:34:42 -06:00
tangxifan 7d059f7407 [Benchmark] Bug fix in dual port ram 16k benchmark 2021-04-27 23:33:20 -06:00
tangxifan 3c1c33bf1e [Benchmark] Add a microbenchmark just fit 16k dual port ram 2021-04-27 22:51:43 -06:00
tangxifan 7e2368158e [Benchmark] move benchmarks to microbenchmark category 2021-04-27 22:12:30 -06:00
tangxifan 5a85ec9fa0 [Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised 2021-04-27 22:09:10 -06:00
tangxifan dd46780865 [Script] Update yosys script using BRAMs 2021-04-27 21:44:27 -06:00
tangxifan fdfbdc4613 [Test] Update task configuration files to use dedicated yosys script 2021-04-27 20:05:04 -06:00
tangxifan 2802b0895c [HDL] Add yosys technology library for reworked architecture using 16k-bit DPRAM 2021-04-27 19:55:46 -06:00
tangxifan e67095edd2 [HDL] Add 16k-bit dual port ram verilog 2021-04-27 19:55:16 -06:00
tangxifan 0f8aaae2bc [Arch] Patch architecture using 16kbit dual port RAM 2021-04-27 19:54:34 -06:00
tangxifan 1d498bb296 [Benchmark] Add a scalable micro benchmark fifo 2021-04-27 15:26:52 -06:00
tangxifan 6cb4d7d720 [Test] Add the new test to regressiont test 2021-04-27 14:41:38 -06:00
tangxifan b8ced5377f [Test] Add a test case for i/o mapping writer 2021-04-27 14:41:15 -06:00
tangxifan f9fd444b86 [Script] Add an write I/O mapping example script for openfpga shell 2021-04-27 14:40:26 -06:00
tangxifan 1d5e926d9e [Test] Deploy new test to CI 2021-04-26 16:29:54 -06:00
tangxifan 6291871faf [Test] Added a test for the example architecture with 2x2 DSP blocks 2021-04-26 16:28:43 -06:00
tangxifan 8c007c7c49 [Arch] Add a new example architecture where a DSP block occupies a 2x2 grid 2021-04-26 16:28:10 -06:00
tangxifan 7d4c5e3cd1 [Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block 2021-04-26 12:00:57 -06:00
tangxifan 6e87b8875b [Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block 2021-04-26 11:59:25 -06:00
tangxifan b7da22501c [Test] Deply new test to regression test 2021-04-24 15:55:05 -06:00
tangxifan 5adffad602 [Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!! 2021-04-24 15:49:53 -06:00
tangxifan 80f98328df [Test] Update test settings for architecture with fracturable DSP blocks 2021-04-24 15:16:50 -06:00
tangxifan 8b8096f3a8 [HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block 2021-04-24 14:57:09 -06:00
tangxifan a3a98fa21d [Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition 2021-04-24 14:56:10 -06:00
tangxifan 4f454abfde [Arch] Add a new architecture using fracturable 16-bit DSP blocks 2021-04-24 14:01:42 -06:00
tangxifan 272d1fffb7 [HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks 2021-04-24 13:30:46 -06:00
tangxifan ddcdb35b28 [Arch] Bug fix in single-mode 8-bit DSP architectures 2021-04-24 13:30:03 -06:00
tangxifan 1c6b9a23d7 [Test] Add new test for multi-mode 16-bit DSP blocks 2021-04-24 13:29:29 -06:00
tangxifan c44688739d [HDL] Add verilog netlist for the fracturable 16-bit multiplier blocks 2021-04-23 22:12:26 -06:00
tangxifan 09cc7f0007 [Script] Enable constant net routing for heterogeneous FPGAs 2021-04-23 20:44:36 -06:00
tangxifan 189c94ff19 [Test] Deploy new mac benchmarks to tests 2021-04-23 20:44:14 -06:00
tangxifan 200b6d39a6 [Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit 2021-04-23 20:36:28 -06:00
tangxifan 671394ec2c [Benchmark] Add microbenchmarks for mac with different sizes for DSP testing 2021-04-23 20:33:43 -06:00
tangxifan cbb7d41b6e [Script] Enable constant net routing for VTR benchmarks 2021-04-23 14:15:13 -06:00
tangxifan 784713e88a [Test] Add golden results for IWLS2005 as a simple QoR check 2021-04-22 19:27:31 -06:00
tangxifan a16896054d [Script] Enable constant net routing for iwls benchmarks 2021-04-22 19:16:32 -06:00
tangxifan 1dcb8e39a9 [Test] Unlock more IWLS'2005 benchmarks in testing 2021-04-22 09:23:33 -06:00
tangxifan 61a473e479 [Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support 2021-04-21 22:56:19 -06:00
tangxifan 5a519390ff [HDL] Enriched DFF model in yosys technology library 2021-04-21 22:49:05 -06:00
tangxifan ce6018e123 [Arch] Enriched DFF model to support active-low/high FFs 2021-04-21 22:48:31 -06:00
tangxifan adfea88be2 [HDL] Rename multi-mode DFF module 2021-04-21 20:06:03 -06:00
tangxifan 62497549b6 [HDL] Add multi-mode DFF module 2021-04-21 20:04:40 -06:00
tangxifan 3a5c26c6a1 [Test] Update IWLS test by using new architecture and customize DFF techmap 2021-04-21 19:51:25 -06:00
tangxifan 8cbea6a268 [HDL] Add technology library for customizable DFF synthesis 2021-04-21 19:50:51 -06:00
tangxifan 3d615e1516 [Script] Add yosys script supporting customize DFF/BRAM/DSP mapping 2021-04-21 19:50:07 -06:00
tangxifan 9d9840d9b7 [Arch] Add architecture using multi-mode DFFs 2021-04-21 19:49:48 -06:00
tangxifan 8046b16c15 [Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing 2021-04-21 14:04:34 -06:00
tangxifan b203ef7bc2 [Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs 2021-04-21 14:03:51 -06:00
tangxifan 2fa370d7d5 [Test] Patch regression tests for fpga bitstream 2021-04-19 17:15:14 -06:00
tangxifan 64163edbe6 [Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting 2021-04-19 16:15:25 -06:00
tangxifan 578d81b67a [Test] Patch task configuration file 2021-04-19 16:15:00 -06:00
tangxifan 18eb5c9de9 [Test] Deploy new test to CI 2021-04-19 15:56:41 -06:00
tangxifan 5976cc0a1c [Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection 2021-04-19 15:54:18 -06:00
tangxifan 7018073e28 [Script] Update openfpga shell script w/o ace usage to adapt pin constraint files 2021-04-17 15:04:51 -06:00
tangxifan da95da933b [Test] Add pin constraint file to map reset to correct FPGA pins 2021-04-17 15:04:26 -06:00
tangxifan e3dafe99da [Arch] Revert to old version arch due to editing by mistake 2021-04-16 20:58:32 -06:00
tangxifan c020333512
Merge branch 'master' into dff_techmap 2021-04-16 20:54:28 -06:00
tangxifan 7172fc9ea1 [Test] Patch test for architecture using asynchronous DFFs 2021-04-16 20:48:37 -06:00
tangxifan 0a15f366cb [HDL] Patch dff models used in yosys tech map 2021-04-16 20:48:15 -06:00
tangxifan 16e02ef485 [Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script 2021-04-16 20:47:39 -06:00
tangxifan 1c2f91b7e6 [Script] Patch yosys script with dff tech map 2021-04-16 20:47:18 -06:00
tangxifan 2666726f36 [Script] Remove clock routing from example openfpga shell script without ace 2021-04-16 20:46:49 -06:00
tangxifan 23d08757cf [Script] Add example script without using ACE2 2021-04-16 20:20:10 -06:00
tangxifan bbdc0e53af [Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures 2021-04-16 20:14:48 -06:00
tangxifan b11d03f9c5 [Test] Deploy new test to CI 2021-04-16 20:01:40 -06:00
tangxifan 93be81abe1 [Test] Add test case for architecture using DFF with reset 2021-04-16 20:00:48 -06:00
tangxifan 5414a6a3da [Script] Add yosys script with custom DFF tech mapping 2021-04-16 20:00:30 -06:00
tangxifan 4239bb4e68 [Arch] Patch architecture files using multi-mode DFFs 2021-04-16 19:59:55 -06:00
tangxifan f2f7f010ea [Arch] Add new architectures using DFF with reset in VPR 2021-04-16 19:26:18 -06:00
tangxifan 64294ae4eb [Doc] Update README for architecture files due to new architecture features 2021-04-16 19:25:54 -06:00
tangxifan ff4460695b [HDL] Add dff tech map files for yosys 2021-04-16 17:00:55 -06:00
tangxifan e46c6e75a3 [Benchmark] Add missing RTL for IWLS2005 benchmarks 2021-04-16 16:50:41 -06:00
tangxifan 87587bbb74 [Test] Add iwls2005 benchmarks to regression tests 2021-04-16 16:12:05 -06:00
tangxifan 1566a5558a [Test] Add task configuration file for iwls2005 2021-04-16 16:10:31 -06:00
tangxifan 43bf016576 [Script] Add example openfpga shell script for iwls benchmark 2021-04-16 16:09:47 -06:00
tangxifan 26d3b5a954 [Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches 2021-04-16 16:08:58 -06:00
tangxifan 86ad572530 [Benchmark] Add opencore RTLs from IWLS 2005 benchmarks 2021-04-16 14:27:54 -06:00
tangxifan b469705819
Merge branch 'master' into fpga_sdc_test 2021-04-11 21:14:46 -06:00
tangxifan 1db8bd7eec [Test] Update regression test with new SDC tests 2021-04-11 20:24:32 -06:00
tangxifan 07f6066c11 [Script] Update timing unit in SDC example script 2021-04-11 20:24:18 -06:00
tangxifan 94c4c817eb [Test] Expand sdc time unit test to sweep all the available units 2021-04-11 20:14:09 -06:00
tangxifan a4893e27cf [Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification 2021-04-11 17:26:27 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
tangxifan b00b4f0f5f [HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian 2021-03-23 15:44:53 -06:00
tangxifan d82ffe0cbf [Test] Deploy MAC_8 benchmark to regression test 2021-03-23 15:36:28 -06:00
tangxifan 108c84a022 [HDL] Add HDL for 8-bit single-mode multiplier 2021-03-23 15:36:09 -06:00
tangxifan 145a80de43 [Script] Add an openfpga shell script for heterogeneous fpga verification 2021-03-23 15:35:34 -06:00
tangxifan fdec72b5bc [Arch] Add an example architecture with 8-bit single-mode multiplier 2021-03-23 15:35:06 -06:00
tangxifan be03eafd66 [Benchmark] Add a micro benchmark: 8-bit multiply and accumulate 2021-03-23 15:33:37 -06:00
tangxifan 8c970a792a [Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier 2021-03-23 15:33:00 -06:00
tangxifan 6b0409da60 [Script] Add a template yosys script support only DSP mapping 2021-03-23 15:32:10 -06:00
tangxifan a4bbffd1aa [HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA 2021-03-23 15:30:41 -06:00
tangxifan fff16a01ab [Test] Update tolerance when checking VTR benchmark QoR 2021-03-23 12:27:20 -06:00
tangxifan 781880ed93 [Script] Add tolerance options to check qor script 2021-03-23 12:26:33 -06:00
tangxifan e3f8a6cf7a [Test] Deploy QoR check to VTR benchmark regression test 2021-03-23 11:15:22 -06:00
tangxifan 351dec5935 [Test] Add QoR csv file for vtr benchmarks 2021-03-23 11:15:02 -06:00
tangxifan 23e7f7f1f5 [Script] Update default list of result extraction for openfpga flow 2021-03-23 11:06:42 -06:00
tangxifan adfbd28a7a [Script] Add a simple QoR checker 2021-03-23 11:06:16 -06:00
tangxifan 61eddb08de [Test] Update task configuration by commenting out high-runtime VTR benchmarks 2021-03-22 14:42:42 -06:00
tangxifan 55d1004cf2 [Benchmark] Add missing DPRAM module to LU32PEEng 2021-03-22 14:41:38 -06:00
tangxifan 5fc83ebea3 [Benchmark] Add missing DPRAM modules to LU8PEEng 2021-03-22 14:38:00 -06:00
tangxifan b828f91a78 [Benchmark] Add missing DPRAM and SPRAM modules to mcml 2021-03-22 14:13:05 -06:00
tangxifan d050f1b746 [Script] Enable fast bitstream generation for VTR benchmarks 2021-03-22 12:54:36 -06:00
tangxifan 4bfd0c0a02 [Test] Enable more VTR benchmark in testing 2021-03-22 12:53:30 -06:00
tangxifan b906ab814e [Benchmark] Add missing DPRAM module to mkPktMerge 2021-03-22 12:51:23 -06:00
tangxifan 310c2a9495 [Benchmark] Add missing DPRAM module to mkDelayWorker32B 2021-03-22 12:51:02 -06:00
tangxifan 707247283c [Benchmark] Add missing DPRAM module to mkSMAdapter4B 2021-03-22 12:50:39 -06:00
tangxifan eb056e2afd [Benchmark] Add missing DPRAM module to or1200 2021-03-22 12:50:17 -06:00
tangxifan 7fd345a616 [Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs 2021-03-22 10:39:47 -06:00
tangxifan cc10b10703 [Test] Enable more benchmarks for testing; See problems when mapping BRAMs 2021-03-20 22:53:37 -06:00
tangxifan 169ee53b79 [Benchmark] Add missing modules to VTR benchmarks 2021-03-20 22:53:17 -06:00
tangxifan eca2a35612 [Script] Add route chan width option to vtr openfpga script 2021-03-20 22:00:09 -06:00
tangxifan 9a3aff274f [Test] Use fix routing channel width to save runtime for VTR benchmarks 2021-03-20 21:59:44 -06:00
tangxifan ca9a70fc88 [Test] Comment out benchmarks have problems in synthesis 2021-03-20 21:29:21 -06:00
tangxifan 125e94a6b3 [Test] Add full VTR benchmark (with most commented); ready for massive testing 2021-03-20 21:01:18 -06:00
tangxifan 2bd8ef2af9 [Benchmark] Patch boundtop.v with missing SPRAM module 2021-03-20 21:00:53 -06:00
tangxifan cb07848475 [Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation 2021-03-20 18:11:54 -06:00
tangxifan f3792bc6f6 [Test] Update VTR benchmark test case to include DSP example benchmark 2021-03-20 18:09:19 -06:00
tangxifan 477a522885 [HDL] Rename tech lib to be consistent with arch name changes 2021-03-20 18:08:03 -06:00
tangxifan 911979a731 [Arch] Update heterogenous architecture for vtr benchmark by adding mult36 2021-03-20 18:04:59 -06:00
tangxifan 1185f7b8bf [Script] Add a template yosys script to enable DSP mapping 2021-03-20 17:05:30 -06:00
tangxifan 6bf4880c50 [benchmark] Add vtr benchmark 2021-03-17 15:24:26 -06:00
tangxifan f9dc7c1b54 [HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells 2021-03-17 15:15:22 -06:00
tangxifan 08a86e056a [Test] Add vtr benchmark regression test 2021-03-17 15:13:58 -06:00
tangxifan 7eeb35d21f [Script] Bug fix in yosys script to synthesis BRAM 2021-03-17 15:12:04 -06:00
tangxifan 1976a8068f [Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added) 2021-03-17 15:11:17 -06:00
tangxifan deee7ba366 [Script] Add example script to run vtr benchmarks 2021-03-17 15:10:56 -06:00
tangxifan 910f8471dd [Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys) 2021-03-17 15:10:05 -06:00
tangxifan 76113a80fa [HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture 2021-03-17 15:09:12 -06:00
tangxifan e1f8b252b1 Merge branch 'master' into yosys_heterogeneous_block_support 2021-03-16 20:05:21 -06:00
tangxifan d12a8a03fd [Test] Update test case using yosys bram parameters 2021-03-16 19:52:17 -06:00
tangxifan 094b3e9b90 [Script] Use parameters in template yosys script supporting BRAMs 2021-03-16 19:51:48 -06:00
tangxifan cea43c2c45 [HDL] Add SPRAM module to generic yosys tech lib for openfpga usage 2021-03-16 18:04:31 -06:00
tangxifan 73b06256d0 [Test] Deploy the new yosys script supporting BRAM to regression tests 2021-03-16 16:52:59 -06:00
tangxifan 84778bd38d [Script] Add new yosys script to support architectures with BRAMs 2021-03-16 16:52:18 -06:00
tangxifan 090f483a11 [Script] Now task-run script support the use of env variables openfpga_path in yosys scripts 2021-03-16 16:45:57 -06:00
tangxifan 76837e02e6 [Script] Rename yosys script supporting bram and restructure techlib files 2021-03-16 16:16:53 -06:00
tangxifan e61857aa2b
Merge branch 'master' into ganesh_dev 2021-03-11 19:17:02 -07:00
tangxifan 366bec232c [Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI 2021-03-11 15:25:48 -07:00
tangxifan bb2a02c9ad [HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v] 2021-03-11 15:23:14 -07:00
tangxifan baf162e401 [Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification 2021-03-10 22:45:19 -07:00
tangxifan a6186db315 [Test] Update bitstream annotation with new syntax 2021-03-10 20:45:17 -07:00
tangxifan 7d07f5d8cb [Test] Update bitstream setting example with mode bit overwriting 2021-03-10 15:34:53 -07:00
tangxifan b42541d84e [Flow] Support multiple iterations in rewriting yosys scripts 2021-03-10 14:10:35 -07:00
tangxifan 90a00da1df [Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset' 2021-03-10 13:56:35 -07:00
tangxifan d21909ad6c [Test] Use custom rewriting script in lut_adder test 2021-03-10 13:48:20 -07:00
tangxifan 0e772bc3b4 [Script] Patch the yosys rewrite script to avoid existing blif outputs 2021-03-10 13:47:30 -07:00
tangxifan 7adb78b159 [Script] Add a template yosys script with rewriting at the end 2021-03-10 13:40:31 -07:00
tangxifan 035043d0d8 [Script] Revert to the state that post synthesis verilog is not required for yosys_vpr 2021-03-10 13:36:11 -07:00
tangxifan 5d46537b5b [Script] Allow users to specify custom post-synthesis verilog for simulation 2021-03-10 11:45:55 -07:00
tangxifan aafd87c3f9 [Flow] Update flow-run to support custom yosys rewrite scripts 2021-03-10 11:36:29 -07:00
Tarachand Pagarani db8ea86b2f update tests to use no_ff_map and remove tests that need async set/reset for now 2021-03-10 10:04:45 -08:00
Tarachand Pagarani 608bd1f658 comment out desings that utilize local async reset/preset 2021-03-09 19:24:01 -08:00
Tarachand Pagarani 7f4c20ff33 comment out desings that utilize local async reset/preset 2021-03-09 10:37:06 -08:00
Tarachand Pagarani c4b83aeaa9 bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type 2021-03-09 00:46:40 -08:00
tangxifan 2daa770319 [Arch] Update openfpga architecture to include quicklogic cell sim 2021-03-08 21:40:29 -07:00
tangxifan 812d8c950e [Script] Update quicklogic's script to output correct verilog file name 2021-03-08 21:39:44 -07:00
tangxifan 37aa42d305 [Test] Patch task configuration file for lut_adder_test to use correct rewrite script 2021-03-08 21:38:51 -07:00
tangxifan c53c41b7a5 [Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file 2021-03-08 21:09:23 -07:00
tangxifan 131643dcc0 [Flow] Bug fix for yosys rewrite function in openfpga flow-run script 2021-03-08 21:08:55 -07:00
ganeshgore b860722893
Fixed parameter ys_rewrite_params name bug 2021-03-08 10:34:39 -07:00
ganeshgore 52de55e7eb
Merge branch 'master' into ganesh_dev 2021-03-08 10:15:06 -07:00
tangxifan 906d2fa72d
Merge branch 'master' into shift_reg 2021-03-08 09:24:29 -07:00
Ganesh Gore 7a35811430 [Flow] Yosys rewrite support 2021-03-08 00:35:47 -07:00
Ganesh Gore 67cd9a69b7 [Flow] Extended yosys variable subtitution 2021-03-08 00:21:07 -07:00
Lalit Sharma 7945628307 Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification 2021-03-07 22:25:01 -08:00
Lalit Sharma 6a1ce01084 Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-07 22:02:11 -08:00
Tarachand Pagarani ce76c58422 add shift register test case 2021-03-05 09:06:05 -08:00
Lalit Sharma 2b2acae757 Adding command to generate verilog file out of yosys run 2021-03-05 04:07:02 -08:00
Lalit Sharma 0cbad747a1 Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family 2021-03-04 01:10:47 -08:00
Lalit Sharma 817729ac86 Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables 2021-03-01 22:31:15 -08:00
tangxifan e34380a654
Merge branch 'master' into default_net_type 2021-03-01 08:38:58 -07:00
Lalit Sharma ea4aee8cb2 For time-being yosys script running in no_adder mode. 2021-02-28 22:07:23 -08:00
Lalit Sharma 0038496d9c Replacing -openfpga with -family qlf_k4n8 2021-02-28 21:08:47 -08:00
tangxifan b4b6ada06f [Script] Correct bugs in example scripts using default_net_type 2021-02-28 16:31:44 -07:00
tangxifan 86930d63d3 [Test] Deploy new test to CI 2021-02-28 16:18:46 -07:00
tangxifan b90a17543d [Test] Add new test case to test default nettype in different verilog syntax 2021-02-28 16:16:45 -07:00
tangxifan 9f4d05da67 [Test] Bug fix for new test case 2021-02-28 16:11:30 -07:00
tangxifan 8cc2c7d924 [Script] Bug fix for default net type example script 2021-02-28 12:35:44 -07:00
tangxifan 6d419fed41 [Test] Deploy verilog default net wire type test case to CI 2021-02-28 12:33:48 -07:00
tangxifan 18a7041424 [Test] Add default net type test for explicit port mapping 2021-02-28 12:31:32 -07:00
tangxifan 0723b79bce [Script] Add example script for verilog default net type 2021-02-28 12:29:56 -07:00
tangxifan 27200e3daa [Test] Update regression test cases for fpga verilog 2021-02-28 12:24:36 -07:00
tangxifan ff29cc3dff [Test] Move tests to a test group 2021-02-28 12:23:35 -07:00
tangxifan 9cb1ca42fe [Test] Deploy default net type option to test case 2021-02-28 12:20:43 -07:00
tangxifan ae05871b1f [Script] Remove default net type from an example script; Limit it to some test cases 2021-02-28 12:19:14 -07:00
tangxifan d7eb159726 [Script] Add default net type option to example openfpga shell scripts 2021-02-28 12:08:30 -07:00
tangxifan 0d82e4939c [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00
tangxifan 744d87cb4e [Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues 2021-02-26 09:34:52 -07:00
tangxifan 870d3a0e27 Merge branch 'master' into dev 2021-02-26 09:28:42 -07:00
Lalit Sharma 1082d3c677 Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys 2021-02-25 23:39:07 -08:00
Lalit Sharma 1e48d4f6dc Modifying custom yosys script file name 2021-02-25 22:21:39 -08:00
tangxifan 4c2a88e27f [Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed 2021-02-24 11:51:10 -07:00
tangxifan 0ce9b66c75 [Arch] Add a dummy adder lut circuit model to support HDL simulation 2021-02-24 10:09:44 -07:00
tangxifan 86a602d381 [Test] Deploy new test to CI 2021-02-23 19:55:07 -07:00
tangxifan a62786986b [Test] Turn off verification in adder lut test temporarily 2021-02-23 19:03:25 -07:00
tangxifan ad25944e59 [Arch] Patched superLUT architecture example when trying adder8 synthesis script 2021-02-23 19:00:27 -07:00
tangxifan 53df7f69e7 [Test] Bug fix in the test case using lut adder 2021-02-23 16:59:46 -07:00
tangxifan db71cc8a16 [Test] Add LUT adder test using quicklogic synthesis script 2021-02-23 16:50:58 -07:00
tangxifan 19f6b221b1 [Test] Rework comments on runtime 2021-02-22 15:25:57 -07:00
tangxifan 4803b0ce42 [Test] Add test case for sdc controller 2021-02-22 15:02:14 -07:00
tangxifan c7a9a4e896 [Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs 2021-02-22 15:01:50 -07:00
tangxifan ca135f3325 [Arch] Add flagship architecture with 8-clock 2021-02-22 15:01:18 -07:00
tangxifan 2e2b1cb6e7 [Test] Use hetergenenous FPGA architecture in quicklogic tests 2021-02-22 13:41:04 -07:00
tangxifan 1c09c55e9f [Arch] Add hetergenenous 8-clock FPGA architecture 2021-02-22 13:38:50 -07:00
tangxifan b3fed683f9 [Test] Deploy test to CI 2021-02-22 12:43:30 -07:00
tangxifan bc30f62c5a [Test] Add test for sdc controller 2021-02-22 12:41:53 -07:00
tangxifan 60dc194d8f [Test] Bug fix in the 5clock test case 2021-02-22 11:46:23 -07:00
tangxifan 71e0026a50 [Test] Add new test for 5-clock counter to quicklogic tests 2021-02-22 11:32:17 -07:00
tangxifan 2bb588dacf [Flow] Add a new script for generating bitstream for multi-clock architectures 2021-02-22 11:31:24 -07:00
tangxifan 77896379e2 [Arch] Add simulation setting for 8-clock architectures 2021-02-22 11:10:03 -07:00
tangxifan 16debe49f6 [Arch] Add more comments on the 4 clock simulation setting file 2021-02-22 11:04:34 -07:00
tangxifan 0ac75723af [Arch] Add new architecture with 8 clocks 2021-02-22 11:00:45 -07:00
tangxifan b9c2564a7e [Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks 2021-02-22 10:49:21 -07:00
tangxifan bc8aa0ebc6 [Test] Remove routing test from quicklogic's flow test 2021-02-22 10:22:47 -07:00
tangxifan 2dbdc2644f [Benchmark] Remove replicate micro benchmarks 2021-02-22 10:22:19 -07:00
tangxifan 9b6b2068ee [Test] Move MCNC test to benchmark sweep test group 2021-02-22 10:18:34 -07:00