Commit Graph

1083 Commits

Author SHA1 Message Date
tangxifan 3f9afea3e8 add preconfig testbench test case for memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 288294c23a add fast configuration test case for memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 73d4c835b7 add regression test case for memory bank 2020-06-11 19:31:13 -06:00
tangxifan a1ec6833c2 add memory bank example arch xml 2020-06-11 19:31:13 -06:00
tangxifan 2def059b5b add standalone configuration protocol to pre config test cases 2020-06-11 19:31:12 -06:00
tangxifan 5f6a790eff add new test cases for the standalone memory configuration protocol 2020-06-11 19:31:12 -06:00
tangxifan 8b5b221a21 add new architecture for standalone memory organization 2020-06-11 19:31:12 -06:00
tangxifan a5138113e4 add fast configuration testcase 2020-06-11 19:31:12 -06:00
tangxifan 8b3e79766c add fast configuration option to fpga_verilog to speed up full testbench simulation 2020-06-11 19:31:12 -06:00
tangxifan 05aa166a9e add preconfig testbench cases to regression tests for different configuration protocols 2020-06-11 19:31:11 -06:00
tangxifan 827e2e6713 file moving in regression tests 2020-06-11 19:31:11 -06:00
tangxifan b5e5182f52 frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops 2020-06-11 19:31:11 -06:00
tangxifan 583c15131b change configuration latch to be triggered at negative edge; Frame-based fabric passed Modelsim verification but failed in iVerilog 2020-06-11 19:31:11 -06:00
tangxifan 6a72c66eb8 bug fixed for frame-based configuration memory in top-level full testbench 2020-06-11 19:31:11 -06:00
tangxifan f5968fda52 add configurable latch Verilog codes 2020-06-11 19:31:10 -06:00
tangxifan 1e73fd6def create configuration frame example script 2020-06-11 19:31:10 -06:00
tangxifan 3a0d3b4e95 fix the broken CI/regression tests due to incorrect file path 2020-06-11 19:31:10 -06:00
tangxifan 3fa3b17061 start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches. 2020-06-11 19:31:10 -06:00
tangxifan bba476fef4 add explicit port mapping support to Verilog testbench generator 2020-06-11 19:31:07 -06:00
tangxifan 910be3cadb massively deploy disable_timing for configure ports in CI 2020-06-11 19:31:06 -06:00
tangxifan 13f591cacf add new command to disable timing for configure ports of programmable modules 2020-06-11 19:31:06 -06:00
tangxifan fc2b09514e add configuration chain write to regression tests 2020-06-11 19:31:06 -06:00
tangxifan 1943929353 add write_fabric_hierarchy to regression tests 2020-06-11 19:31:04 -06:00
tangxifan 98fbcb5410 add time unit test for SDC generation to CI 2020-06-11 19:31:04 -06:00
tangxifan 4083fae41a add new test cases about user-defined simulation settings 2020-06-11 19:31:03 -06:00
tangxifan 2fbf9c2cfc change to a higher simulation clock speed to accelerate CI verification.
Later, we should place simulation information in another XML so that we can reuse that easily
2020-06-11 19:31:03 -06:00
tangxifan 889bc8dbe8 add more test cases about LUT design and deploy to CI 2020-06-11 19:31:02 -06:00
tangxifan 889f179ce7 add local encoder test case 2020-06-11 19:31:01 -06:00
tangxifan 98a658a013 bug fixed in routing_test.v. Deployed to regression tests 2020-06-11 19:31:01 -06:00
tangxifan 6dd8d347e1 try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif 2020-06-11 19:31:01 -06:00
CHARAS SAMY f6cea1e17c Added test_mode_low benchmark 2020-06-11 19:31:01 -06:00
CHARAS SAMY 3c781b18d3 Added routing benchmark 2020-06-11 19:31:01 -06:00
tangxifan 42cede37fa add testcases on generate fabric/testbench only 2020-06-11 19:31:01 -06:00
tangxifan 9bf91bd92a start testing mcnc_big20 using OpenFPGA tasks 2020-06-11 19:30:55 -06:00
ganeshgore c31b20dc91 Added support for simulation setting file in the task flow 2020-06-11 19:28:13 -06:00
ganeshgore 49edeb119c BugFix : Relative path for refrence benchmark fixed 2020-06-11 19:28:13 -06:00
ganeshgore 890ead91b9 Fixed modelsim include references 2020-06-11 19:28:13 -06:00
ganeshgore c1b73efa62 Added support for simulation setting file in the task flow 2020-06-10 23:12:30 -06:00
ganeshgore a3103f6afe BugFix : Relative path for refrence benchmark fixed 2020-04-25 20:16:17 -06:00
ganeshgore 9d1b3d6865 Fixed modelsim include references 2020-04-24 21:53:57 -06:00
tangxifan 90f608baea changing task mcnc file for debugging (temporarily now) Will be corrected later 2020-04-23 18:58:39 -06:00
tangxifan 417d534121 fine tune mcnc example script to run Modelsim simulations easily 2020-04-23 16:15:45 -06:00
tangxifan df85175765 fine tuning on mcnc example script so that we can run run_modelsim.py --runsim 2020-04-22 21:44:52 -06:00
tangxifan f9fcc6b471 tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation 2020-04-22 18:24:09 -06:00
tangxifan 726185cd5e add test cases using spypad architecture 2020-04-22 12:56:57 -06:00
tangxifan 73e9006372 add arch file with spy pads 2020-04-22 12:56:09 -06:00
tangxifan 9fb8971281 add FPGA arch with spypads to portofilo 2020-04-22 11:12:28 -06:00
tangxifan 9761d13eef update microbenchmark and2 module name 2020-04-20 13:37:39 -06:00
tangxifan 489ca75230 adapt benchmark and_latch module name to be different than benchmark and 2020-04-20 13:15:05 -06:00
tangxifan f6b7583a2a add tasks for single mode 2020-04-20 12:55:40 -06:00
tangxifan 8b03ec900f fine-tune micro benchmark to fit port mapping in testbenches 2020-04-19 17:05:12 -06:00
tangxifan e10cafe0a5 Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
2020-04-19 16:42:31 -06:00
tangxifan 32ed609238 update micro benchmark set and regression tests using them 2020-04-19 12:49:07 -06:00
tangxifan 98878f474b light change on arch file to accelerate mcnc big20 run 2020-04-19 12:03:31 -06:00
tangxifan cc163081f5 recover mcnc big20 test configuration 2020-04-18 21:06:43 -06:00
tangxifan 2e3a811f4f critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results 2020-04-18 21:04:46 -06:00
tangxifan f76a3090c4 add mcnc big20 test cases and start debugging 2020-04-18 19:25:16 -06:00
tangxifan 95863e996a minor update on arch to use auto layout sizing 2020-04-18 18:43:56 -06:00
tangxifan 2f3a36ee81 update timing and rename the arch file 2020-04-18 18:39:47 -06:00
tangxifan 7ce34be175 update sample architecture timing 2020-04-17 22:06:06 -06:00
tangxifan 2ea4b8a2a2 add more flagship architectures 2020-04-17 19:12:27 -06:00
tangxifan 2ffd174e6a fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI 2020-04-15 15:48:33 -06:00
tangxifan 032ebc29e6 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2020-04-15 12:53:20 -06:00
tangxifan 1e742a3676 add test case on auto-check test benches 2020-04-15 12:52:52 -06:00
ganeshgore 689c4a3e19 BugFix: The filename in the previous commit 2020-04-15 12:44:22 -06:00
tangxifan 46fe1e84ce Merge branch 'dev' into ganesh_dev 2020-04-15 12:27:51 -06:00
ganeshgore 7f37bf1441 Added formal verification support to fpga_flow script 2020-04-15 12:24:51 -06:00
tangxifan 7ba3e27371 add duplicated_grid_pin test case to Travis CI 2020-04-12 20:10:51 -06:00
tangxifan e78643f108 add flatten routing test case to Travis CI 2020-04-12 20:06:40 -06:00
tangxifan 59ea0a6ad5 add implicit verilog test case to Travis CI 2020-04-12 20:00:20 -06:00
tangxifan 23aef96d3a add behavioral verilog test case to Travis CI 2020-04-12 19:55:47 -06:00
tangxifan 11e9014542 add notes about debugging the aib FPGA 2020-04-12 19:07:53 -06:00
tangxifan a614e5aad9 add long adder chain to Travis CI 2020-04-12 15:43:19 -06:00
tangxifan f71a85a1d4 add test cases on different routing multiplexer circuit designs to Travis CI 2020-04-12 15:39:45 -06:00
tangxifan 214d98fbcd add register chain and scan chain to Travis CI 2020-04-12 15:28:22 -06:00
tangxifan 148cc74d6a add io test cases to Travis CI 2020-04-12 15:01:47 -06:00
tangxifan da5af8f0e0 try to add aib test case. bug found 2020-04-12 14:54:45 -06:00
tangxifan 28cb412359 add test case of wide BRAM 16k to Travis CI 2020-04-12 14:37:08 -06:00
tangxifan 5d665aa04b reshape bram test case 2020-04-12 14:32:09 -06:00
tangxifan 600a48edc7 add test case of BRAM to Travis CI 2020-04-12 14:27:05 -06:00
tangxifan 2444752de8 add untileable test case to Travis CI 2020-04-12 14:08:24 -06:00
tangxifan d806ad3148 add testcases using openfpga_shell in openfpga_flow 2020-04-12 12:54:21 -06:00
tangxifan 68fd296e14 add more test vpr architecture to regression tests 2020-04-12 12:49:16 -06:00
ganeshgore 80bdb41df6 Updated task file to run formal verification 2020-04-11 18:30:21 -06:00
tangxifan 49ddbf98c3 add more testing architecture to openfpga_flow 2020-04-11 18:01:09 -06:00
tangxifan 130b78ca74 update arch in openfpga_flow 2020-04-11 18:00:37 -06:00
ganeshgore f6b3c5854a Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
2020-04-11 16:45:22 -06:00
ganeshgore 8ea272dc2c Patched the OpenFPGA shell execution bug 2020-04-08 21:28:14 -06:00
ganeshgore 583a4d8767 Fixed bug in openfpga_flow script 2020-04-08 12:04:08 -06:00
ganeshgore e1db4df744 Created task for FPGA shell run 2020-04-06 00:35:07 -06:00
ganeshgore ea4122a8a4 Updated openfpga_flow and task file to support sheel run 2020-04-06 00:34:36 -06:00
ganeshgore 7f98ecc8a6 OpenFPGA shell run test script template 2020-04-06 00:32:43 -06:00
ganeshgore eb3b02277a Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
ganeshgore 77f7e13ba7 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2020-04-05 20:59:10 -06:00
ganeshgore d1d3446568 backedup partial upgrade for fpga_flow script 2020-04-05 11:36:24 -06:00
tangxifan 2f38b5cbc2 Merge branch 'refactoring' into dev 2020-03-08 16:23:20 -06:00
tangxifan b219b096ee hotfix on removing dangling inputs from GSB, which are CLB direct output 2020-03-08 13:54:49 -06:00
AurelienUoU c51001c853 Add compilation verification task in openfpga_flow 2020-01-23 13:13:23 -07:00
ganeshgore cd69f1870d Merge remote-tracking branch 'origin/ganesh_dev' into dev 2020-01-23 10:07:36 -07:00
ganeshgore 46bb5ef9d0 Added disp option in openfpga_flow, Default is --nodisp 2020-01-23 10:04:38 -07:00
AurelienUoU 85c9f26a9f Update documentation about cmake version and graphical interface 2020-01-22 20:46:49 -07:00
ganeshgore f0bed1244c Added blif file folding before VPR run 2020-01-09 16:50:34 -07:00
ganeshgore 74b650e9e1 Added fpga_x2p_duplicate_grid_pin option 2019-12-30 12:25:28 -07:00
ganeshgore d1e260f54f Spice related option added 2019-12-30 12:16:04 -07:00
tangxifan ef9ed2ccbc added duplicate_grid_pin test case 2019-12-26 15:08:31 -07:00
AurelienUoU 09fd2afa9c Adding heterogeneous synthesis requirements 2019-12-03 16:09:26 -07:00
AurelienUoU 32176eb352 Adding EPFL benchmark task for openfpga_flow 2019-12-03 14:31:53 -07:00
AurelienUoU 2f14716f13 Adding DPRAM behavioural Verilog netlist and its TB 2019-12-03 13:58:20 -07:00
tangxifan 96733f9ea8 add minor comments in task file for modelsim regression tests 2019-11-16 22:34:03 -07:00
Ganesh Gore 3f235a16f9 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-11-16 19:14:34 -07:00
Ganesh Gore 6bb11918dc Updated modelsim and collected result 2019-11-16 19:10:04 -07:00
tangxifan a13f406918 tweaking mcnc_big20 task run for modelsim 2019-11-16 18:00:55 -07:00
Ganesh Gore 00ec36c1af Added Modelsim error check in log 2019-11-16 13:18:13 -07:00
Ganesh Gore 373dbe0718 First draft for multithreaded Modelsim simulation 2019-11-16 01:06:09 -07:00
Ganesh Gore f05aede868 Added task support for modelsim script 2019-11-15 23:23:15 -07:00
Ganesh Gore f52eaef622 Updated flow script and skipped travis upload on failure test setup. 2019-11-15 14:35:15 -07:00
tangxifan 4df6402241 add python script for batch simulations 2019-11-15 14:23:03 -07:00
tangxifan d391983e8c passing regression test on dpram benchmarks 2019-11-07 14:57:46 -07:00
tangxifan 56b4ee008e add test for heterogeneous FPGA and fix bugs 2019-11-06 17:45:11 -07:00
tangxifan 4ea5756be6 bug fixed for std cell MUX2 architecture and add the case to regression tests 2019-11-06 16:06:47 -07:00
tangxifan 09eb373a6e bug fixing for autocheck top testbench where clock port is not default names 2019-11-06 12:21:20 -07:00
tangxifan 00280b835e reorganize regression tests 2019-11-05 16:31:42 -07:00
tangxifan 7952d134b9 add tree-like mux test case to regression test 2019-11-05 16:24:39 -07:00
tangxifan a308a13d7c use prefix instead of lib_name when building modules, then use lib_name for standard cell modules 2019-11-05 15:41:59 -07:00
tangxifan 0ec465d4e1 refactoring auto-check top Verilog testbench 2019-11-03 17:41:29 -07:00
tangxifan dc241e6c03 add explicit port mapping support in testbenches; remove dangling ports in benchmarks 2019-11-02 23:03:47 -06:00
Ganesh Gore a880802803 Bug Fix: Corrected read VPR stat filename 2019-11-01 20:51:05 -06:00
tangxifan e2b042c61c Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-11-01 18:27:27 -06:00
Ganesh Gore 370a5ed408 Bug Fix: shifter ff.v include path to tcl script 2019-11-01 18:22:40 -06:00
Ganesh Gore 595d2d3070 Simple argument shuffle 2019-11-01 18:21:26 -06:00
Ganesh Gore 27005d6640 Added Modelsim Python Script 2019-11-01 18:20:40 -06:00
tangxifan 49bfb3223c add compact routing to regression test 2019-11-01 10:53:47 -06:00
tangxifan 531cc064fc bug fixing for formal top-level testbench 2019-11-01 10:47:40 -06:00
Ganesh Gore da0778e813 Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev 2019-11-01 00:46:34 -06:00
tangxifan d709868463 adding more regression tests which is quick run but very helpful for debugging 2019-10-31 20:17:40 -06:00
tangxifan a6a3e7c36b adding mcnc_big20 to regression test 2019-10-31 19:31:27 -06:00
Ganesh Gore 81180939ca Bug fix: Missing exit_if_fail flag in fpga_flow script 2019-10-31 09:56:57 -06:00
tangxifan 5531422186 update regression test with no-explicit port mapping cases 2019-10-30 19:37:06 -06:00
tangxifan 55fbd72293 many bugs have been fixed 2019-10-30 15:50:42 -06:00
tangxifan 4398cffaaa single mode is working, multi-mode is under debugging 2019-10-29 22:32:36 -06:00
tangxifan 10491c4291 bring single mode test case online with bug fixing 2019-10-28 17:04:10 -06:00
tangxifan 5cb3717433 add single mode test case to regression test. debugging now 2019-10-28 15:57:17 -06:00
Ganesh Gore c034b871bb Made activity file independent of power option 2019-10-15 16:08:25 -06:00
Ganesh Gore eaf8ecee86 added _vpr.txt subscript to vpr log files 2019-10-15 16:07:34 -06:00
Baudouin Chauviere 027272c976 Faster regression test 2019-10-05 12:10:55 -06:00
Baudouin Chauviere db059af8b8 Lighten the regression test 2019-10-03 13:33:28 -06:00
Baudouin Chauviere c7e1f7d90b Added explicit_verilog to regression test in a clean way 2019-10-03 10:17:04 -06:00
Baudouin Chauviere 33e50bbc8c fix 2019-10-01 16:54:16 -06:00
Baudouin Chauviere 7c3ab38410 Hot fix 2019-10-01 16:40:16 -06:00
Ganesh Gore 069f628bb0 Merge branch 'dev' of github.com:LNIS-Projects/OpenFPGA into ganesh_dev 2019-09-28 11:21:37 -06:00
Ganesh Gore d269472daf Updated formality python script 2019-09-27 14:00:57 -06:00
AurelienUoU feddcbcb21 Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-09-23 11:41:38 -06:00
tangxifan 5efea159c5 Simplify part of regression test to min_route_chan_width 2019-09-22 11:14:33 -06:00
Ganesh Gore 1dffe54807 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-22 00:21:25 -06:00
Ganesh Gore 50039a4b6e Added remove run directory option 2019-09-21 23:35:56 -06:00
AurelienUoU cc0bfdd548 Add testcase in regression test for architecture with 1 IO cell/IO block 2019-09-20 10:27:26 -06:00
tangxifan 4e7af5cdc5 update tileable_routing test 2019-09-18 15:59:32 -06:00
tangxifan 0f0d06aad7 add non-LUT intermediate buffer to test and apply minor bug fix 2019-09-18 15:04:51 -06:00
Ganesh Gore 8afcba2c45 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-18 12:15:42 -06:00
Ganesh Gore cd5fd6ce6c Added explicit checking to VVP execution 2019-09-18 12:14:26 -06:00
Ganesh Gore 56c40ca06d Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-17 22:12:11 -06:00
Ganesh Gore 169732ccc1 Added verbose option in VVP output 2019-09-17 22:09:37 -06:00
tangxifan d7ac7d3649 start refactoring the switch block verilog generation 2019-09-17 20:40:26 -06:00
Ganesh Gore 7be83235a0 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-16 21:25:26 -06:00
Ganesh Gore 678e3181ba Made compact_routing_hierarchy options uncond 2019-09-16 21:22:13 -06:00
tangxifan 5abbfd6a0f add tileable routing to regression test 2019-09-16 20:45:02 -06:00
Ganesh Gore 81b9c5b266 Added flag for VVP exit code 2019-09-14 12:35:47 -06:00
Ganesh Gore d90329678a Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-09-14 12:11:36 -06:00
Ganesh Gore ec3854a648 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-14 00:14:17 -06:00
Ganesh Gore e5c99c8b12 Quick terminate on fail added 2019-09-13 23:56:38 -06:00
Ganesh Gore bd9e57bc37 Added better task name 2019-09-13 23:30:42 -06:00
Ganesh Gore a6e592247e Replaced options exit_on fail and show_thread logs 2019-09-13 22:50:20 -06:00
Ganesh Gore d64bb18346 Separated Modelsim tcl script generation 2019-09-07 12:36:22 -04:00
Ganesh Gore d55b7e9497 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-06 11:49:38 -04:00
Ganesh Gore bcbcd463fe Added pending runs in log 2019-09-06 11:48:13 -04:00
Ganesh Gore 9abc1e1e7d Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-05 13:12:41 -04:00
Ganesh Gore 702a7683a8 Ensure strict exit of fpga_flow on error 2019-09-05 10:23:35 -06:00
tangxifan d2d750a15c debugged rram mux branch Verilog generation 2019-09-02 16:21:29 -06:00
Ganesh Gore 48ec1eefcd Added fpga_task cmd options in doc [ci skip] 2019-09-02 02:45:05 -06:00
Ganesh Gore e37ac1a565 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-09-02 00:19:19 -06:00
Ganesh Gore 241b001282 Added openfpga_task doc 2019-09-01 22:15:53 -06:00
Ganesh Gore ad4c688206 Added print for JobID to architecture mapping 2019-08-31 22:04:57 -06:00
Ganesh Gore f4e99c150a resolve missing variable bug 2019-08-31 21:55:32 -06:00
Ganesh Gore 3d4f7f66fd Updated to run with python3 2019-08-31 21:42:31 -06:00
Ganesh Gore 06c0dbb328 Added docuementation for fpga_flow 2019-08-31 15:19:34 -06:00
Ganesh Gore 02137805c7 Added python version check in flow and task scripts 2019-08-29 22:14:30 -06:00
Ganesh Gore a25124b58c Added additional PATH variables 2019-08-29 21:37:07 -06:00
Ganesh Gore f54a8522fa Log prints task stats 2019-08-27 22:04:32 -06:00
Ganesh Gore 903c2b7705 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-08-27 21:38:17 -06:00
Ganesh Gore 715adc13ff Failed result do not throw error 2019-08-27 21:25:38 -06:00
tangxifan 94538b5062 add more testing architecture 2019-08-27 18:44:58 -06:00
tangxifan f04565386f refactored behavioral mux branch verilog generation 2019-08-27 18:39:25 -06:00
tangxifan de8a6bc833 update regression tests 2019-08-26 21:00:15 -06:00
Ganesh Gore 7a3ff94116 Added blif task in travis script 2019-08-25 01:28:21 -06:00
Ganesh Gore 937ebd1b85 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-08-25 00:53:18 -06:00
Ganesh Gore 632c9d6976 Added python execution path in config file 2019-08-25 00:42:48 -06:00
Ganesh Gore f558437ae1 Added task for vpr_blif flow 2019-08-25 00:23:39 -06:00
tangxifan 3fb3082447 add more tests 2019-08-23 14:10:01 -06:00
Ganesh Gore 52d6a9e979 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-08-23 13:41:29 -06:00
Ganesh Gore 28dde899db Updated Architecture Template 2019-08-23 12:44:45 -06:00
tangxifan 520630c5e2 add more testing tasks 2019-08-23 10:16:52 -06:00
Ganesh Gore 6e7de16ad4 Solved bug in commnad rearrangement 2019-08-22 23:41:25 -06:00
Ganesh Gore 89589ddc1c Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-08-22 18:46:51 -06:00
Ganesh Gore 77e2a7bca3 Added execution time logs in flow script 2019-08-22 17:01:38 -06:00
Ganesh Gore 30cbe38d3d Added Test Modes - Added blif VPR Option 2019-08-22 17:00:59 -06:00
Ganesh Gore d5ce1b557e Made thread logs prettier 2019-08-22 16:56:58 -06:00
Ganesh Gore 764d7039b5 Import utils bug fixing for travis test 2019-08-21 12:42:58 -06:00
Ganesh Gore 2f0acfad23 Updated travis to run regression task 2019-08-21 11:09:53 -06:00
Ganesh Gore e51ff44710 Added execution time information in logs 2019-08-21 11:08:47 -06:00
Ganesh Gore a335a57c6c Added debug option to commnad line arguments 2019-08-21 11:08:13 -06:00
tangxifan 59f1ac7310 add missing files and try to refactor submodule essential 2019-08-20 20:49:26 -06:00
tangxifan 5f55fc7b49 add missing files and developing essential gates 2019-08-20 20:43:46 -06:00
tangxifan 60e8d2b29f add missing files and try to refactor submodule essential 2019-08-20 16:13:08 -06:00
Ganesh Gore b7484ef178 Removed traces of old template file 2019-08-20 15:58:19 -06:00
Ganesh Gore afee2229af Removed unused templates and file from openfpga_flow directory 2019-08-19 21:32:52 -06:00
Ganesh Gore 08b0ef3550 Updated validate_command_line_arguments function
+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
2019-08-19 21:28:23 -06:00
Ganesh Gore 53941eaf5c Changed yosys output file name 2019-08-19 19:06:46 -06:00
Ganesh Gore 8d0153d34e Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
Ganesh Gore 616d7706c9 Added list of intermidiate files filename 2019-08-19 19:05:08 -06:00
Ganesh Gore 8f8707ff98 Added option to filter results after parsing 2019-08-19 19:04:14 -06:00
Ganesh Gore 5116aa2ae1 Added architecture and replaced variables 2019-08-19 19:02:50 -06:00
Ganesh Gore cb5b16c949 Moved required files to openfpga folder 2019-08-19 18:57:42 -06:00
Ganesh Gore 6dc05b769b Added Power Model Files 2019-08-19 18:55:23 -06:00
Ganesh Gore 7f6c1b3e00 Code re-arrangement
+ Added support for subdirectory task in openfpga_task
+ Rearranged function order
+ Combined vpr re-route and standrad run function
+ Removed external_call function from fpga_flow script
+ Added .gitignore to task directory
2019-08-18 12:26:05 -06:00
Ganesh Gore 12c998c12a Added dockerignore + minor changes in openfpga_flow script 2019-08-17 16:22:52 -06:00
Ganesh Gore 66bb8a5e4b Updated RRAM architecture file 2019-08-17 02:20:04 -06:00
Ganesh Gore 7bfc48b8e4 Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
Ganesh Gore c43c3cdf25 Added VPR output parse option 2019-08-16 13:36:39 -06:00
Ganesh Gore effbd332aa Added task report generation 2019-08-16 10:59:44 -06:00
Ganesh Gore 901932a4fc First draft: Working openfpga task flow 2019-08-16 09:44:50 -06:00
Ganesh Gore 5d3708651e Added fpga_flow and fpga_task script
+ Missed local intermediate commits
2019-08-15 14:39:58 -06:00
Ganesh Gore 9ab57d1b2e Added fpga_flow script - Working Yosys 2019-08-09 16:49:05 -06:00
Ganesh Gore b82369dd96 Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00