Added openfpga_task doc
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Ganesh Gore
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@ -12,10 +12,15 @@ Welcome to OpenFPGA's documentation!
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motivation
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.. toctree::
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:caption: Getting Started
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:caption: Getting Started
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eda_flow
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run_fpga_flow
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run_fpga_task
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.. toctree::
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:maxdepth: 2
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:caption: Tools Guide
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@ -37,10 +42,10 @@ Welcome to OpenFPGA's documentation!
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.. toctree::
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:maxdepth: 2
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:caption: Appendix
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contact
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reference
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For more information on the VTR see vtr_doc_ or vtr_github_
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For more information on the Yosys see yosys_doc_ or yosys_github_
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@ -1,6 +1,6 @@
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.. _run_fpga_flow:
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run_fpga_flow
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OpenFPGA Flow
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---------------
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This python script executes the supported OpenFPGA flow for a
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@ -33,6 +33,8 @@ where:
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All the benchmark files provided will be copied to ``tmp/bench`` directory without maintaining any directory structure.
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**Users should ensure that no important files are kept in this directory as script will clear directory before each execution**
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.. _openfpga-variables:
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OpenFPGA Variables
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~~~~~~~~~~~~~~~~~~
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Frequently, while running OpenFPGA flow User is suppose to refer external files.
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@ -178,4 +180,4 @@ The OpenFPGA Flow configuration file consists of following sections
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[Not implemented yet]
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Default OpenFPGA_flow Configuration file is located in ``open_fpga_flow\misc\fpgaflow_default_tool_path.conf``.
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User-supplied configuration file overrides or extends the default configuration.
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User-supplied configuration file overrides or extends the default configuration.
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@ -0,0 +1,213 @@
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.. _run_fpga_task:
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OpenFPGA Task
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---------------
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Tasks provide a framework for running the :ref:`run_fpga_flow` on
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multiple benchmarks, architectures and set of OpenFPGA parameters.
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The structure of the framework is very similar to
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`VTR-Tasks <https://docs.verilogtorouting.org/en/latest/vtr/tasks/>`_
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implementation with additional functionality and minor file extention changes.
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Task Directory
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~~~~~~~~~~~~~~
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The tasks are store in a ``TASK_DIRECTORY``, which by default points to
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``${OPENFPGA_PATH}/openfpga_flow/tasks``. Every directory or sub-directory in
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task directory consisting of ``../config/task.conf`` file can be reffered as a
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task.
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To create as task name called ``basic_flow`` following directory has to exist::
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${TASK_DIRECTORY}/basic_flow/conf/task.conf
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Similarly ``regression/regression_quick`` expect following structure::
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${TASK_DIRECTORY}/regression/regression_quick/conf/task.conf
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Running OpenFPGA Task:
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~~~~~~~~~~~~~~~~~~~~~~
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At a minimum ``open_fpga_flow.py`` requires following command-line arguments::
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open_fpga_flow.py <task1_name> <task2_name> ...
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where:
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* ``<task_name>`` is the name of the task to run
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Craeating A New OpenFPGA Task:
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Create the folder ``${TASK_DIRECTORY}/<task_name>`` and create a file called
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``${TASK_DIRECTORY}/<task_name>/config/task.conf`` in it.
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Configuring a New Task
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~~~~~~~~~~~~~~~~~~~~~~
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The task configuration file ``task.conf`` consists of ``GENERAL``,
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``ARCHITECTURES``, ``BENCHMARKS``, ``SYNTHESIS_PARAM`` and
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``SCRIPT_PARAM_<var_name>`` sections.
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Declaring all the above sections are mandatory.
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.. note::
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Configuration file supports all the OpenFPGA Variables refer
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:ref:`openfpga-variables` section to know more. Variables in configuration
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file is declares as ``${PATH:<variable_name>}``
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General Section
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^^^^^^^^^^^^^^^
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.. option:: fpga_flow==<yosys_vpr|vpr_blif>
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Defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.
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.. option:: power_analysis=<true|false>
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Specifies whether to perform power analysis or not.
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.. option:: power_tech_file=<path_to_tech_XML_file>
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Declares which tech XML file to be used while perforing Power Analysis.
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.. option:: spice_output=<true|false>
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Setting up this variable generates Spice Netlist at the end of the flow.
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Equivalent of passing ``--vpr_fpga_spice`` command to :ref:`run_fpga_flow`
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.. option:: verilog_output=<true|false>
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Setting up this variable generates Verilog Netlist at the end of the flow.
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Equivalent of passing ``--vpr_fpga_spice`` command to :ref:`run_fpga_flow`
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.. option:: timeout_each_job=<true|false>
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Specifies the the timeout for each :ref:`run_fpga_flow` execution. Default
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is set to ``20 min``
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Architectures Sections
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^^^^^^^^^^^^^^^^^^^^^^
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User can define the list of architecure files in this section.
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.. option:: arch<arch_label>=<xml_architecture_file_path>
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The ``arch_label`` variable can be any number of string without
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white-spaces. ``xml_architecture_file_path`` is path to the actual XML
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architecture file
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.. note::
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In final OpenFPGA Task result the architecture will be referred by its
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``arch_label``.
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Benchmarks Sections
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^^^^^^^^^^^^^^^^^^^
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User can define the list of benchmarks files in this section.
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.. option:: bench<bench_label>=<list_of_files_in_benchmark>
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The ``bench_label`` variable can be any number of string without
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white-spaces. ``xml_architecture_file_path`` is path to the actual XML
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architecture file
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For Example following code shows how to define a benchmarks,
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with single file multiple files and files added from specific directory.
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.. code-block:: text
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[BENCHMARKS]
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# To declare single benchmark file
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bench_design1=${BENCH_PATH}/design/top.v
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# To declare multiple benchmark file
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bench_design2=${BENCH_PATH}/design/top.v,${BENCH_PATH}/design/sub_module.v
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# To add all files in specific directory to the benchmark
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bench_design3=${BENCH_PATH}/design/top.v,${BENCH_PATH}/design/lib/*.v
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.. note::
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``bench_label`` is referred again in ``Synthesis_Param`` section to
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provide addional information about benchmark
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Synthesis Parameter Sections
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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User can define extra parameters for each benchmark defined in the
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``BENCHMARKS`` sections.
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.. option:: bench<bench_label>_top=<Top_Module_Name>
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This defines the Top Level module name for ``bench_label`` benchmark.
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By default, the top level module name is cosidereed as a ``top``.
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.. option:: bench<bench_label>_yosys_tmpl=<yosys_template_file>
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[TODO]
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.. option:: bench<bench_label>_chan_width=<chan_width_to_use>
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In case of running fixed channel width routing for each benchmark,
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this option defines the channel width to be used for ``bench_label``
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benchmark
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.. option:: bench<bench_label>_act=<activity_file_path>
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In case of running ``blif_vpr_flow`` this option provides the activity files
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to be used to generate testbench for ``bench_label`` benchmark
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.. option:: bench<bench_label>_verilog=<source_verilog_file_path>
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In case of running ``blif_vpr_flow`` with verification this option provides
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the source verilog design for ``bench_label`` benchmark to be used
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while verification.
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Script Parameter Sections
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^^^^^^^^^^^^^^^^^^^^^^^^^
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The script parameter section lists set of commnad line pararmeters to be passed to :ref:`run_fpga_flow` script. The section name is defines as ``SCRIPT_PARAM_<parameter_set_label>`` where `parameter_set_label` can be any word without white spaces.
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The section is referred with ``parameter_set_label`` in final result file.
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For example following code Specifies the two sets (``Fixed_Routing_30`` and ``Fixed_Routing_50``) of :ref:`run_fpga_flow` arguments.
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.. code-block:: text
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[SCRIPT_PARAM_Fixed_Routing_30]
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# Execute fixed routing with channel with 30
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fix_route_chan_width=30
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[SCRIPT_PARAM_Fixed_Routing_50]
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# Execute fixed routing with channel with 50
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fix_route_chan_width=50
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Example Task Configuration File
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. code-block:: text
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[GENERAL]
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spice_output=false
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verilog_output=false
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power_analysis = true
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power_tech_file = ${PATH:TECH_PATH}/winbond90nm/winbond90nm_power_properties.xml
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timeout_each_job = 20*60
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[ARCHITECTURES]
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arch0=${PATH:ARCH_PATH}/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
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[BENCHMARKS]
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bench0=${PATH:BENCH_PATH}/MCNC_Verilog/s298/s298.v
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bench1=${PATH:BENCH_PATH}/MCNC_Verilog/elliptic/elliptic.v
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[SYNTHESIS_PARAM]
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bench0_top = s298
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bench1_top = elliptic
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[SCRIPT_PARAM_Slack_30]
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min_route_chan_width=1.3
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[SCRIPT_PARAM_Slack_80]
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min_route_chan_width=1.8
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@ -160,6 +160,7 @@ def generate_each_task_actions(taskname):
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GeneralSection = task_conf["GENERAL"]
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# Check if specified architecture files exist
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# TODO Store it as a dictionary and take reference from the key
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archfile_list = []
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for _, arch_file in task_conf["ARCHITECTURES"].items():
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arch_full_path = arch_file
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