Added VPR output parse option
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@ -71,7 +71,7 @@ parser.add_argument('--ace_p', type=float,
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parser.add_argument('--black_box_ace', action='store_true')
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# VPR Options
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parser.add_argument('--min_route_chan_width', type=int,
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parser.add_argument('--min_route_chan_width', type=float,
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help="Turn on min_route_chan_width")
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parser.add_argument('--max_route_width_retry', type=int, default=100,
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help="Maximum iterations to perform to reroute")
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@ -350,6 +350,7 @@ def run_yosys_with_abc():
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lut_size = max([int(pb_type.find("input").get("num_pins"))
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for pb_type in root.iter("pb_type")
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if pb_type.get("class") == "lut"])
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logger.info("Extracted lut_size size from arch XML = %s", lut_size)
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logger.info("Running Yosys with lut_size = %s", lut_size)
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except:
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logger.exception("Failed to extract lut_size from XML file")
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@ -491,11 +492,11 @@ def run_vpr():
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# Minimum routing channel width
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if (args.min_route_chan_width):
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logger.info("Executing minimum channel width routing")
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min_channel_width *= 1+(args.min_route_chan_width/100)
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min_channel_width *= args.min_route_chan_width
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min_channel_width = int(min_channel_width)
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min_channel_width += 1 if (min_channel_width % 2) else 0
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logger.info("Trying to route using %d channels" % min_channel_width)
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logger.info(("Trying to route using %d channels" % min_channel_width) +
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" (Slack of %d%%)" % ((args.min_route_chan_width-1)*100))
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while(1):
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res = run_vpr_route(args.top_module+"_ace_corrected_out.blif",
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@ -607,7 +608,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile):
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if args.vpr_fpga_verilog_include_signal_init:
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command += ["--fpga_verilog_include_signal_init"]
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if args.vpr_fpga_verilog_formal_verification_top_netlist:
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command += ["--fpga_verilog_formal_verification_top_netlist"]
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command += ["--fpga_verilog_print_formal_verification_top_netlist"]
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if args.vpr_fpga_verilog_print_modelsim_autodeck:
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command += ["--fpga_verilog_print_modelsim_autodeck",
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args.vpr_fpga_verilog_print_modelsim_autodeck]
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@ -676,7 +677,8 @@ def run_vpr_route(bench_blif, fixed_chan_width, logfile):
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"--net_file", args.top_module+"_vpr.net",
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"--place_file", args.top_module+"_vpr.place",
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"--route_file", args.top_module+"_vpr.route",
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"--full_stats", "--nodisp"
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"--full_stats", "--nodisp",
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"--route"
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]
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if args.power:
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command += [
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@ -734,8 +736,9 @@ def run_vpr_route(bench_blif, fixed_chan_width, logfile):
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if process.returncode:
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logger.info("Standard VPR run failed with returncode %d",
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process.returncode)
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except:
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except Exception as e:
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logger.exception("Failed to run VPR")
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process_failed_vpr_run(e.output)
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clean_up_and_exit("")
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logger.info("VPR output is written in file %s" % logfile)
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return chan_width
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@ -852,10 +855,15 @@ def external_call(parent_logger=None, passed_args=[]):
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main()
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def process_failed_vpr_run(vpr_output):
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for line in vpr_output.split("\n"):
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if "error" in line.lower():
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logger.error("-->>" + line)
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if __name__ == "__main__":
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# Setting up print and logging system
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logging.basicConfig(level=logging.INFO, stream=sys.stdout,
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format='%(levelname)s (%(threadName)-9s) - %(message)s')
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format='%(levelname)s - %(message)s')
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logger = logging.getLogger('OpenFPGA_Flow_Logs')
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# Parse commandline argument
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@ -246,7 +246,7 @@ def run_single_script(s, command):
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universal_newlines=True)
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output.write(process.stdout)
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except:
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logger.exception()
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logger.exception("Failed to launch openfpga flow")
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logger.info("%s Finished " % name)
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@ -280,8 +280,6 @@ def collect_results(job_run_list):
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result["name"] = run["name"]
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task_result.append(result)
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pprint.pprint(task_result)
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with open("task_result.csv", 'w', newline='') as csvfile:
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writer = csv.DictWriter(csvfile, fieldnames=task_result[0].keys())
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writer.writeheader()
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