Added additional PATH variables
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@ -50,6 +50,11 @@ args = parser.parse_args()
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task_script_dir = os.path.dirname(os.path.abspath(__file__))
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script_env_vars = ({"PATH": {
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"OPENFPGA_FLOW_PATH": task_script_dir,
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"ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"),
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"BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"),
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"TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"),
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"SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"),
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"VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"),
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"OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir,
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os.pardir))}})
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config = ConfigParser(interpolation=ExtendedInterpolation())
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@ -153,7 +158,7 @@ def generate_each_task_actions(taskname):
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# Get Flow information
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logger.info('Running "%s" flow' %
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GeneralSection.get("fpga_flow", fallback="yosys_vpr"))
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GeneralSection.get("fpga_flow", fallback="yosys_vpr"))
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# Check if specified benchmark files exist
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benchmark_list = []
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@ -184,7 +189,6 @@ def generate_each_task_actions(taskname):
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CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width",
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fallback=chan_width_common)
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if GeneralSection.get("fpga_flow") == "vpr_blif":
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# Check if activity file exist
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if not SynthSection.get(bech_name+"_act"):
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