Moved required files to openfpga folder
This commit is contained in:
Ganesh Gore
parent
6dc05b769b
commit
cb5b16c949
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@ -8,7 +8,7 @@ abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
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abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
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vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr
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ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace
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pro_blif_path = ${PATH:OPENFPGA_PATH}/fpga_flow/scripts/pro_blif.pl
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pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl
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iverilog_path = iverilog
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include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists
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@ -0,0 +1,447 @@
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#!usr/bin/perl -w
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use strict;
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#use Shell;
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use FileHandle;
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#Use the time
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use Time::gmtime;
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#Get Date
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my $mydate = gmctime();
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my ($char_per_line) = (80);
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my ($fname,$frpt,$finitial);
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my $add_default_clk = "off";
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my $latch_token;
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my ($remove_buffers) = (0);
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my ($default_clk_name) = ("clk");
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my @buffers_to_remove;
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my @buffers_to_rename;
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sub print_usage()
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{
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print "Usage:\n";
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print " perl <script_name.pl> [-options]\n";
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print " Options:(Mandatory!)\n";
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print " -i <input_blif_path>\n";
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print " -o <output_blif_path>\n";
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print " Options: (Optional)\n";
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print " -remove_buffers\n";
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print " -add_default_clk\n";
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print " -initial_blif <input_blif_path>\n";
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print "\n";
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return 0;
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}
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sub opts_read()
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{
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if (-1 == $#ARGV) {
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print "Error: No input argument!\n";
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&print_usage();
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exit(1);
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} else {
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for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++) {
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if ("-i" eq $ARGV[$iargv]) {
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$fname = $ARGV[$iargv+1];
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} elsif ("-o" eq $ARGV[$iargv]) {
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$frpt = $ARGV[$iargv+1];
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} elsif ("-add_default_clk" eq $ARGV[$iargv]) {
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$add_default_clk = "on";
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} elsif ("-initial_blif" eq $ARGV[$iargv]) {
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$finitial = $ARGV[$iargv+1];
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} elsif ("-remove_buffers" eq $ARGV[$iargv]) {
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$remove_buffers = 1;
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}
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}
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}
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return 0;
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}
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# Print a line of blif netlist
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sub fprint_blifln($ $ $) {
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my ($FH, $tokens_ref, $char_per_line) = @_;
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my ($cur_line_len) = (0);
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my @tokens = @$tokens_ref;
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if ($char_per_line < 1) {
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die "ERROR: (fprint_blifln) minimum acceptable number of chars in a line is 1!\n";
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}
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# if the length of current line exceed the char_per_line,
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# A continue line '\' is added and start a new line
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for (my $itok = 0; $itok < ($#tokens+1); $itok++) {
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if (!($tokens[$itok])) {
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next;
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}
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# Contain any buffer names to be removed won't show up
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if (1 == $remove_buffers) {
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for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) {
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if ($tokens[$itok] eq $buffers_to_remove[$ibuf]) {
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$tokens[$itok] = $buffers_to_rename[$ibuf];
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}
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}
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}
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$cur_line_len += length($tokens[$itok]);
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if ($cur_line_len > $char_per_line) {
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print $FH "\\"."\n";
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$cur_line_len = 0;
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}
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print $FH "$tokens[$itok] ";
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$cur_line_len += length($tokens[$itok]);
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}
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print $FH "\n";
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}
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sub read_blifline($ $) {
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my ($FIN, $line_no_ptr) = @_;
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my ($lines,$line) = ("","");
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# Get one line
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if (defined($line = <$FIN>)) {
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chomp $line;
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$lines = $line;
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# Replace the < and > with [ and ], VPR does not support...
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$lines =~ s/</[/g;
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$lines =~ s/>/]/g;
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while($lines =~ m/\\$/) {
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$lines =~ s/\\$//;
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if (defined($line = <$FIN>)) {
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chomp $line;
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$lines = $lines.$line;
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$line =~ s/</[/g;
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$line =~ s/>/]/g;
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} else {
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return $lines;
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}
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}
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return $lines;
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} else {
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return $lines;
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}
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}
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sub process_blifmodel($ $) {
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my ($FIN,$line_no_ptr) = @_;
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my ($blackbox) = (0);
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my ($lines);
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my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded) = (0,0,0,0);
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my @model_input_tokens;
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my ($input_lines);
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while(!eof($FIN)) {
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# Get one line
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$lines = &read_blifline($FIN,$line_no_ptr);
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# Check the tokens
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if (!defined($lines)) {
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next;
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}
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my @tokens = split('\s+',$lines);
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# .end -> return
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if (!defined($tokens[0])) {
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next;
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}
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if (".end" eq $tokens[0]) {
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return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk);
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} elsif (".inputs" eq $tokens[0]) {
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foreach my $temp(@tokens) {
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if ($temp eq $default_clk_name) {
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$have_default_clk = 1;
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$clk_num++;
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print "Found 1 clock: $temp in @tokens\n";
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last;
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}
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}
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@model_input_tokens = @tokens;
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} elsif (".blackbox" eq $tokens[0]) {
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$blackbox = 1;
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} elsif (".latch" eq $tokens[0]) {
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# illegal definition exit
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if ((3 != $#tokens)&&(5 != $#tokens)) {
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die "ERROR: [LINE: $$line_no_ptr]illegal definition of latch!\n";
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} elsif (3 == $#tokens) {
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# We need a default clock
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if ($need_default_clk == 0) {
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$need_default_clk = 1;
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$clk_num++;
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}
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} elsif (5 == $#tokens) {
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$clk_recorded = 0;
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# Check if we have this clk names already
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foreach my $tmp(@model_input_tokens) {
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if ($tmp eq $tokens[4]) {
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$clk_recorded = 1;
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last;
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}
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}
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# if have been recorded, we push it into the array
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if (0 == $clk_recorded) {
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$clk_num++;
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push @model_input_tokens,$tokens[4];
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}
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}
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# Could be subckt or .names
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} elsif (".names" eq $tokens[0]) {
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if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) {
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# We want to know is this a buffer???
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my $lut_lines = &read_blifline($FIN,$line_no_ptr);
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my @lut_lines_tokens = split('\s+',$lut_lines);
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if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) {
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# push it to the array: buffers_to_remove
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push @buffers_to_remove,$tokens[1];
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push @buffers_to_rename,$tokens[2];
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}
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}
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}
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}
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# Re-organise the input lines
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#print @model_input_tokens;
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$input_lines = ".inputs ";
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foreach my $temp(@model_input_tokens) {
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if (".inputs" ne $temp) {
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$input_lines .= $temp." ";
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}
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}
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$input_lines =~ s/\s+$//;
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@model_input_tokens = split('\s+',$input_lines);
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return (\@model_input_tokens,$blackbox,$clk_num,$have_default_clk,$need_default_clk);
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}
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sub scan_blif()
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{
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my ($line,$lines);
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my @tokens;
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my ($clk_num,$have_default_clk,$need_default_clk,$clk_recorded);
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my ($blackbox,$model_clk_num);
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my @input_tokens;
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my $input_lines;
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my (@input_buffer);
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my ($line_no) = (0);
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if (!defined($finitial)) {
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$latch_token = "re clk";
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} else {
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my $latch_token_found = 0;
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my $count = 0;
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my ($FIN0) = FileHandle->new;
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if ($FIN0->open("< $finitial")) {
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print "INFO: Parsing $finitial...\n";
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} else {
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die "ERROR: Fail to open $finitial!\n";
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}
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while((!$latch_token_found)&&(!eof($FIN0))){
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# Get one line
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$lines = &read_blifline($FIN0);
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if (!defined($lines)) {
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next;
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}
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@tokens = split('\s+',$lines);
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if(".latch" eq $tokens[0]) {
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if($#tokens == 5){
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$latch_token = "$tokens[3] $tokens[4]";
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$latch_token_found = 1;
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}
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}
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}
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close($FIN0);
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}
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# Pre-process the netlist
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# Open src file first-scan to check if we have clock
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my ($FIN) = FileHandle->new;
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if ($FIN->open("< $fname")) {
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print "INFO: Parsing $fname...\n";
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} else {
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die "ERROR: Fail to open $fname!\n";
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}
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while(!eof($FIN)) {
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# Get one line
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$lines = &read_blifline($FIN);
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if (!defined($lines)) {
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next;
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}
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@tokens = split('\s+',$lines);
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if (!defined($tokens[0])) {
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next;
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}
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# When we found .model we should check it. until .end comes.
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# Check if it is a black box
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if (".model" eq $tokens[0]) {
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($input_lines,$blackbox,$model_clk_num,$have_default_clk,$need_default_clk) = &process_blifmodel($FIN,\$line_no);
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if (0 == $blackbox) {
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@input_tokens = @$input_lines;
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}
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$clk_num += $model_clk_num;
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}
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}
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close($FIN);
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# Add default clock
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if ("on" eq $add_default_clk) {
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print "INFO: $clk_num clock ports need to be added.\n";
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print "INFO: have_default_clk: $have_default_clk, need_default_clk: $need_default_clk\n";
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if ((0 == $have_default_clk)&&(1 == $need_default_clk)) {
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push @input_tokens,$default_clk_name;
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}
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}
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# Bypass some sensitive tokens
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for(my $itok = 0; $itok < $#input_tokens+1; $itok++) {
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if ("unconn" eq $input_tokens[$itok]) {
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delete $input_tokens[$itok];
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}
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}
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# Print Buffer names to be removed
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my $num_buffer_to_remove = $#buffers_to_remove + 1;
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print "INFO: $num_buffer_to_remove buffer to be removed:\n";
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for(my $itok = 0; $itok < $#buffers_to_remove+1; $itok++) {
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print $buffers_to_remove[$itok]." will be renamed to ".$buffers_to_rename[$itok]."\n";
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}
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# Second scan - write
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my ($inputs_written) = (0);
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my ($FIN2) = FileHandle->new;
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if ($FIN2->open("< $fname")) {
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print "INFO: Parsing $fname the second time...\n";
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} else {
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die "ERROR: Fail to open $fname!\n";
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}
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# Open des file
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my ($FOUT) = (FileHandle->new);
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if (!($FOUT->open("> $frpt"))) {
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die "Fail to create output file: $frpt!\n";
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}
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while(!eof($FIN2)) {
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$line = <$FIN2>;
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chomp $line;
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if ($line eq "") {
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print $FOUT "\n";
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next;
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}
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# Replace the < and > with [ and ], VPR does not support...
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$line =~ s/</[/g;
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$line =~ s/>/]/g;
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# Check if this line start with ".latch", which we cares only
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@tokens = split('\s+',$line);
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if ((".inputs" eq $tokens[0])&&(0 == $inputs_written)) {
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$lines = $line;
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while($lines =~ m/\\$/) {
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$line = <$FIN2>;
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chomp $line;
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# Replace the < and > with [ and ], VPR does not support...
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$line =~ s/</[/g;
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$line =~ s/>/]/g;
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$lines =~ s/\\$//;
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$lines = $lines.$line;
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}
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#print @input_tokens."\n";
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&fprint_blifln($FOUT,\@input_tokens,$char_per_line);
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$inputs_written = 1;
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next;
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}
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if (".outputs" eq $tokens[0]) {
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$lines = $line;
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while($lines =~ m/\\$/) {
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$line = <$FIN2>;
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chomp $line;
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# Replace the < and > with [ and ], VPR does not support...
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$line =~ s/</[/g;
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$line =~ s/>/]/g;
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$lines =~ s/\\$//;
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$lines = $lines.$line;
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}
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my @output_tokens = split('\s',$lines);
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for(my $itok = 0; $itok < $#output_tokens+1; $itok++) {
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if ("unconn" eq $output_tokens[$itok]) {
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delete $output_tokens[$itok];
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}
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}
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&fprint_blifln($FOUT,\@output_tokens,$char_per_line);
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next;
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}
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if (".latch" eq $tokens[0]) {
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# check if we need complete it
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if ($#tokens == 3) {
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# Complete it
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for (my $i=0; $i<3; $i++) {
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print $FOUT "$tokens[$i] ";
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}
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print $FOUT "$latch_token $tokens[3]\n";
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} elsif ($#tokens == 5) {
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# replace the clock name with clk
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for (my $i=0; $i < ($#tokens+1); $i++) {
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# if (4 == $i) {
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# print $FOUT "clk ";
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# } else {
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print $FOUT "$tokens[$i] ";
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# }
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}
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print $FOUT "\n";
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} else {
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die "ERROR: [LINE: $line_no]illegal definition of latch!\n";
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}
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next;
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} elsif (".names" eq $tokens[0]) {
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if ((3 == ($#tokens + 1))&&(1 == $remove_buffers)) {
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# We want to know is this a buffer???
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my $lut_lines = &read_blifline($FIN2,\$line_no);
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my @lut_lines_tokens = split('\s+',$lut_lines);
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if ((2 == ($#lut_lines_tokens + 1))&&("1" eq $lut_lines_tokens[0])&&("1" eq $lut_lines_tokens[1])) {
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# pass it.
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next;
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} else {
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print $FOUT "$line\n";
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print $FOUT "$lut_lines\n";
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}
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} else {
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print $FOUT "$line\n";
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}
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next;
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} elsif ((".subckt" eq $tokens[0])&&(1 == $remove_buffers)) {
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$lines = $line;
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$lines =~ s/\s+$//;
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while($lines =~ m/\\$/) {
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$line = <$FIN2>;
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chomp $line;
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# Replace the < and > with [ and ], VPR does not support...
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$line =~ s/</[/g;
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$line =~ s/>/]/g;
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$lines =~ s/\\$//;
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$lines = $lines.$line;
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$lines =~ s/\s+$//; #ODIN II has some shit space after \ !!!!!
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}
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my @subckt_tokens = split('\s+',$lines);
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for(my $itok = 0; $itok < $#subckt_tokens+1; $itok++) {
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if (($itok > 1)&&("" ne $subckt_tokens[$itok])) {
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my @port_tokens = split('=',$subckt_tokens[$itok]);
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for (my $ibuf = 0; $ibuf < $#buffers_to_remove + 1; $ibuf++) {
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if ($port_tokens[1] eq $buffers_to_remove[$ibuf]) {
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$port_tokens[1] = $buffers_to_rename[$ibuf];
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}
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}
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$subckt_tokens[$itok] = join ('=',$port_tokens[0],$port_tokens[1]);
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#print "See:".$subckt_tokens[$itok]."\n";
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}
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}
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&fprint_blifln($FOUT,\@subckt_tokens,$char_per_line);
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next;
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}
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print $FOUT "$line\n";
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}
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close($FIN2);
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close($FOUT);
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return 0;
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}
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sub main()
|
||||
{
|
||||
&opts_read();
|
||||
&scan_blif();
|
||||
return 0;
|
||||
}
|
||||
|
||||
&main();
|
||||
exit(0);
|
||||
Loading…
Reference in New Issue